Mark Alan Erle

Person

South Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Combined binary/decimal fixed-point multiplier and method
- Patent number 8,577,952
- Issue date Nov 5, 2013
- International Business Machines Corporation
- Mark Alan Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Execution of fixed point instructions using a decimal floating poin...
- Patent number 8,572,141
- Issue date Oct 29, 2013
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct decimal number tripling in binary coded adders
- Patent number 8,417,761
- Issue date Apr 9, 2013
- International Business Machines Corporation
- Mark Alan Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection using parity compensation in binary coded decimal a...
- Patent number 8,286,061
- Issue date Oct 9, 2012
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scheme to optimize scan chain ordering in designs
- Patent number 7,721,171
- Issue date May 18, 2010
- International Business Machines Corporation
- Mark A. Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for binary leading zero counting with constant...
- Patent number 6,779,008
- Issue date Aug 17, 2004
- International Business Machines Corporation
- Mark Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for summing multiple binary vectors
- Patent number 6,549,927
- Issue date Apr 15, 2003
- International Business Machines Corporation
- Mark Alan Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault simulation using dynamically alterable behavioral models
- Patent number 6,170,078
- Issue date Jan 2, 2001
- International Business Machines Corporation
- Mark A. Erle
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical fault modeling system and method
- Patent number 5,796,990
- Issue date Aug 18, 1998
- International Business Machines Corporation
- Mark Alan Erle
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ERROR DETECTION USING PARITY COMPENSATION IN BINARY CODED DECIMAL A...
- Publication number 20100306632
- Publication date Dec 2, 2010
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Direct Decimal Number Tripling in Binary Coded Adders
- Publication number 20100146031
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Mark Alan Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Binary/Decimal Fixed-Point Multiplier and Method
- Publication number 20100146030
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Mark Alan Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A...
- Publication number 20090240753
- Publication date Sep 24, 2009
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEME TO OPTIMIZE SCAN CHAIN ORDERING IN DESIGNS
- Publication number 20090049353
- Publication date Feb 19, 2009
- International Business Machines Corporation
- Mark A. Erle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Zero detect in partial sums while adding
- Publication number 20060184603
- Publication date Aug 17, 2006
- Son Dao Trong
- G06 - COMPUTING CALCULATING COUNTING

Mark Alan Erle

Person

Patents Grantslast 30 patents

Combined binary/decimal fixed-point multiplier and method

Execution of fixed point instructions using a decimal floating poin...

Direct decimal number tripling in binary coded adders

Error detection using parity compensation in binary coded decimal a...

Scheme to optimize scan chain ordering in designs

Method and apparatus for binary leading zero counting with constant...

Circuit and method for summing multiple binary vectors

Fault simulation using dynamically alterable behavioral models

Hierarchical fault modeling system and method

Patents Applicationslast 30 patents

ERROR DETECTION USING PARITY COMPENSATION IN BINARY CODED DECIMAL A...

Direct Decimal Number Tripling in Binary Coded Adders

Combined Binary/Decimal Fixed-Point Multiplier and Method

METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A...

SCHEME TO OPTIMIZE SCAN CHAIN ORDERING IN DESIGNS

Zero detect in partial sums while adding