Mark Aldo Bordogna

Person

North Andover, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Timestamp alignment for multiple nodes
- Patent number 12,160,495
- Issue date Dec 3, 2024
- Intel Corporation
- Mark Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,805,042
- Issue date Oct 31, 2023
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High accuracy time stamping for multi-lane ports
- Patent number 11,711,159
- Issue date Jul 25, 2023
- Intel Corporation
- Mark Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Timestamp alignment across multiple computing nodes
- Patent number 11,693,448
- Issue date Jul 4, 2023
- Intel Corporation
- Mark Bordogna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for high-precision timestamping of packets
- Patent number 11,671,194
- Issue date Jun 6, 2023
- Intel Corporation
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,546,241
- Issue date Jan 3, 2023
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High accuracy time stamping for multi-lane ports
- Patent number 11,265,096
- Issue date Mar 1, 2022
- Intel Corporation
- Mark Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for high-precision timestamping of packets
- Patent number 11,212,024
- Issue date Dec 28, 2021
- Intel Corporation
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,153,191
- Issue date Oct 19, 2021
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
One-step time stamping of synchronization packets for networked dev...
- Patent number 10,931,391
- Issue date Feb 23, 2021
- Intel Corporation
- Sita Rama Chandrasekhar Mallela
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protected real time clock with hardware interconnects
- Patent number 10,509,435
- Issue date Dec 17, 2019
- Intel Corporation
- Ramamurthy Krithivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet reassembly processing
- Patent number 9,065,761
- Issue date Jun 23, 2015
- Intel Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for circuit emulation services over cell and p...
- Patent number 8,005,094
- Issue date Aug 23, 2011
- Agere Systems Inc.
- Juergen Beck
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for per-port flow control of packets aggregated from multipl...
- Patent number 7,813,285
- Issue date Oct 12, 2010
- Agere Systems Inc.
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for frequency offset control of ethernet packe...
- Patent number 7,593,327
- Issue date Sep 22, 2009
- Agere Systems Inc.
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Forward error correction for high speed optical transmission systems
- Patent number 6,683,855
- Issue date Jan 27, 2004
- Lucent Technologies Inc.
- Mark Aldo Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Control architecture using a multi-layer embedded signal status pro...
- Patent number 6,560,202
- Issue date May 6, 2003
- Lucent Technologies Inc.
- Mark Aldo Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Self-healing networks using virtual rings
- Patent number 6,366,556
- Issue date Apr 2, 2002
- Lucent Technologies Inc.
- James E. Ballintine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for switching signals using an embedded group...
- Patent number 6,301,228
- Issue date Oct 9, 2001
- Lucent Technologies, Inc.
- Mark Aldo Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Control architecture for a homogeneous routing structure
- Patent number 6,137,790
- Issue date Oct 24, 2000
- Lucent Technologies Inc.
- Mark Aldo Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Control of asynchronous transfer mode (ATM) switching networks
- Patent number 6,091,730
- Issue date Jul 18, 2000
- Lucent Technologies Inc.
- Janus Biegaj
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Duplication in asychronous transfer mode (ATM) network fabrics
- Patent number 6,091,731
- Issue date Jul 18, 2000
- Lucent Technologies Inc.
- Janus Biegaj
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Control architecture using an embedded signal status protocol
- Patent number 6,081,503
- Issue date Jun 27, 2000
- Lucent Technologies Inc.
- Mark Aldo Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
PHASE SYNCHRONIZATION BETWEEN TIMERS
- Publication number 20240204899
- Publication date Jun 20, 2024
- Intel Corporation
- Mark BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIME SYNCHRONIZATION TECHNOLOGIES
- Publication number 20230370241
- Publication date Nov 16, 2023
- Intel Corporation
- Daniel Christian BIEDERMAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMESTAMP ALIGNMENT ACROSS MULTIPLE COMPUTING NODES
- Publication number 20230367362
- Publication date Nov 16, 2023
- Intel Corporation
- Mark BORDOGNA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO GENERATE AN EGRESS TIMESTAMP
- Publication number 20230344739
- Publication date Oct 26, 2023
- Surekha Peri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIME DOMAIN MONITORING AND ADJUSTMENT BY A NETWORK INTERFACE DEVICE
- Publication number 20230077631
- Publication date Mar 16, 2023
- Intel Corporation
- Daniel Christian BIEDERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20230016505
- Publication date Jan 19, 2023
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTIPLE TIME DOMAIN NETWORK DEVICE TRANSLATION
- Publication number 20220337683
- Publication date Oct 20, 2022
- Intel Corporation
- Daniel Christian BIEDERMAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OPTICAL AND ELECTRICAL MODULES WITH ENHANCED FEATURES
- Publication number 20220271855
- Publication date Aug 25, 2022
- Intel Corporation
- Daniel Christian BIEDERMAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20220150149
- Publication date May 12, 2022
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS
- Publication number 20220077946
- Publication date Mar 10, 2022
- Intel Corporation
- Mark A. BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMESTAMP ALIGNMENT FOR MULTIPLE NODES
- Publication number 20220006607
- Publication date Jan 6, 2022
- Intel Corporation
- Mark BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR DATA PLANE CONTROL OF NETWORK TIME SYNC PR...
- Publication number 20210211214
- Publication date Jul 8, 2021
- Intel Corporation
- Mark BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS
- Publication number 20210203428
- Publication date Jul 1, 2021
- Intel Corporation
- Mark A. BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS
- Publication number 20210152271
- Publication date May 20, 2021
- Intel Corporation
- Mark BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMESTAMP ALIGNMENT ACROSS MULTIPLE COMPUTING NODES
- Publication number 20200133330
- Publication date Apr 30, 2020
- Intel Corporation
- Mark BORDOGNA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS
- Publication number 20190273571
- Publication date Sep 5, 2019
- Intel Corporation
- Mark BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
One-Step Time Stamping Of Synchronization Packets For Networked Dev...
- Publication number 20190097745
- Publication date Mar 28, 2019
- Intel Corporation
- Sita Rama Chandrasekhar Mallela
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20190044839
- Publication date Feb 7, 2019
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROTECTED REAL TIME CLOCK WITH HARDWARE INTERCONNECTS
- Publication number 20180088625
- Publication date Mar 29, 2018
- Intel Corporation
- Ramamurthy Krithivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRECISE TIMESTAMPING OF ETHERNET PACKETS BY COMPENSATING FOR START-...
- Publication number 20150055644
- Publication date Feb 26, 2015
- LSI Corporation
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRANSMIT REFERENCE SIGNAL CLEANUP WITHIN A SYNCHRONOUS NETWORK APPL...
- Publication number 20140254735
- Publication date Sep 11, 2014
- LSI Corporation
- Shashank Nemawarkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PACKET REASSEMBLY PROCESSING
- Publication number 20130028264
- Publication date Jan 31, 2013
- LSI CORPORATION
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Transparent Mapping of Cell Streams to Packet Services
- Publication number 20100329245
- Publication date Dec 30, 2010
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method For Per-Port Flow Control Of Packets Aggregated From Multipl...
- Publication number 20080291832
- Publication date Nov 27, 2008
- Agere Systems Inc.
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for circuit emulation services over cell and p...
- Publication number 20080002738
- Publication date Jan 3, 2008
- Juergen Beck
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for per-service fault protection and restorati...
- Publication number 20060013210
- Publication date Jan 19, 2006
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for frequency offset control of ethernet packe...
- Publication number 20050041695
- Publication date Feb 24, 2005
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method for flow control of packets aggregated from multiple logical...
- Publication number 20040085904
- Publication date May 6, 2004
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Mark Aldo Bordogna

Person

Patents Grantslast 30 patents

Timestamp alignment for multiple nodes

Technologies for timestamping with error correction

High accuracy time stamping for multi-lane ports

Timestamp alignment across multiple computing nodes

Technologies for high-precision timestamping of packets

Technologies for timestamping with error correction

High accuracy time stamping for multi-lane ports

Technologies for high-precision timestamping of packets

Technologies for timestamping with error correction

One-step time stamping of synchronization packets for networked dev...

Protected real time clock with hardware interconnects

Packet reassembly processing

Method and apparatus for circuit emulation services over cell and p...

Method for per-port flow control of packets aggregated from multipl...

Method and apparatus for frequency offset control of ethernet packe...

Forward error correction for high speed optical transmission systems

Control architecture using a multi-layer embedded signal status pro...

Self-healing networks using virtual rings

Method and apparatus for switching signals using an embedded group...

Control architecture for a homogeneous routing structure

Control of asynchronous transfer mode (ATM) switching networks

Duplication in asychronous transfer mode (ATM) network fabrics

Control architecture using an embedded signal status protocol

Patents Applicationslast 30 patents

PHASE SYNCHRONIZATION BETWEEN TIMERS

TIME SYNCHRONIZATION TECHNOLOGIES

TIMESTAMP ALIGNMENT ACROSS MULTIPLE COMPUTING NODES

METHODS AND APPARATUS TO GENERATE AN EGRESS TIMESTAMP

TIME DOMAIN MONITORING AND ADJUSTMENT BY A NETWORK INTERFACE DEVICE

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

MULTIPLE TIME DOMAIN NETWORK DEVICE TRANSLATION

OPTICAL AND ELECTRICAL MODULES WITH ENHANCED FEATURES

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS

TIMESTAMP ALIGNMENT FOR MULTIPLE NODES

METHOD AND APPARATUS FOR DATA PLANE CONTROL OF NETWORK TIME SYNC PR...

TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS

HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS

TIMESTAMP ALIGNMENT ACROSS MULTIPLE COMPUTING NODES

HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS

One-Step Time Stamping Of Synchronization Packets For Networked Dev...

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

PROTECTED REAL TIME CLOCK WITH HARDWARE INTERCONNECTS

PRECISE TIMESTAMPING OF ETHERNET PACKETS BY COMPENSATING FOR START-...

TRANSMIT REFERENCE SIGNAL CLEANUP WITHIN A SYNCHRONOUS NETWORK APPL...

PACKET REASSEMBLY PROCESSING

Transparent Mapping of Cell Streams to Packet Services

Method For Per-Port Flow Control Of Packets Aggregated From Multipl...

Method and apparatus for circuit emulation services over cell and p...

Method and apparatus for per-service fault protection and restorati...

Method and apparatus for frequency offset control of ethernet packe...

Method for flow control of packets aggregated from multiple logical...