Mark Andrew BRITTAIN

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for controlling access to a memory device
- Patent number 9,785,578
- Issue date Oct 10, 2017
- ARM Limited
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory queue handling techniques for reducing impact of high-latenc...
- Patent number 9,632,954
- Issue date Apr 25, 2017
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory reorder queue biasing preceding high latency operations
- Patent number 8,996,824
- Issue date Mar 31, 2015
- International Business Machines Corporation
- Mark A. Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory reorder queue biasing preceding high latency operations
- Patent number 8,909,874
- Issue date Dec 9, 2014
- International Business Machines Corporation
- Mark A. Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for scheduling memory refresh operations including power states
- Patent number 8,543,759
- Issue date Sep 24, 2013
- International Business Machines Corporation
- Mark A. Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for scheduling memory refresh operations including power...
- Patent number 8,539,146
- Issue date Sep 17, 2013
- International Business Machines Corporation
- Mark A. Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
Power management via DIMM read operation limiter
- Patent number 8,055,922
- Issue date Nov 8, 2011
- International Business Machines Corporation
- Mark Andrew Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
Streaming reads for early processing in a cascaded memory subsystem...
- Patent number 7,934,070
- Issue date Apr 26, 2011
- International Business Machines Corporation
- Mark Andrew Brittain
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
System to provide memory system power reduction without reducing ov...
- Patent number 7,930,469
- Issue date Apr 19, 2011
- International Business Machines Corporation
- Mark A. Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
System to enable a memory hub device to manage thermal conditions a...
- Patent number 7,930,470
- Issue date Apr 19, 2011
- International Business Machines Corporation
- Mark A. Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
System to reduce latency by running a memory channel frequency full...
- Patent number 7,925,824
- Issue date Apr 12, 2011
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to support a full asynchronous interface within a memory hub...
- Patent number 7,925,825
- Issue date Apr 12, 2011
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to increase the overall bandwidth of a memory channel by all...
- Patent number 7,925,826
- Issue date Apr 12, 2011
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double DRAM bit steering for multiple error corrections
- Patent number 7,840,860
- Issue date Nov 23, 2010
- International Business Machines Corporation
- Luiz Carlos Alves
- G11 - INFORMATION STORAGE
Information Patent Grant
Using bit errors from memory to alter memory command stream
- Patent number 7,631,228
- Issue date Dec 8, 2009
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Executing background writes to idle DIMMS
- Patent number 7,600,091
- Issue date Oct 6, 2009
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for memory module power management
- Patent number 7,587,559
- Issue date Sep 8, 2009
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory wrap test mode using functional read/write buffers
- Patent number 7,571,357
- Issue date Aug 4, 2009
- International Business Machines Corporation
- Mark A. Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
Double DRAM bit steering for multiple error corrections
- Patent number 7,523,364
- Issue date Apr 21, 2009
- International Business Machines Corporation
- Luiz Carlos Alves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable bank/timer address folding in memory devices
- Patent number 7,516,264
- Issue date Apr 7, 2009
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory queue with supplemental locations for consecutive addresses
- Patent number 7,493,456
- Issue date Feb 17, 2009
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management via DIMM read operation limiter
- Patent number 7,426,649
- Issue date Sep 16, 2008
- International Business Machines Corporation
- Mark Andrew Brittain
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic power management via DIMM read operation limiter
- Patent number 7,421,598
- Issue date Sep 2, 2008
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Executing background writes to idle DIMMs
- Patent number 7,373,471
- Issue date May 13, 2008
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming reads for early processing in a cascaded memory subsystem...
- Patent number 7,337,293
- Issue date Feb 26, 2008
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for identification and removal of non-timing critical wire r...
- Patent number 6,904,585
- Issue date Jun 7, 2005
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR CONTROLLING ACCESS TO A MEMORY DEVICE
- Publication number 20160357688
- Publication date Dec 8, 2016
- ARM Limited
- Mark Andrew BRITTAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Reorder Queue Biasing Preceding High Latency Operations
- Publication number 20140082272
- Publication date Mar 20, 2014
- IBM Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH-LATENC...
- Publication number 20140052936
- Publication date Feb 20, 2014
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY RECORDER QUEUE BIASING PRECEDING HIGH LATENCY OPERATIONS
- Publication number 20130212330
- Publication date Aug 15, 2013
- IBM Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Scheduling Memory Refresh Operations Including Power States
- Publication number 20130173858
- Publication date Jul 4, 2013
- International Business Machines Corporation
- MARK A. BRITTAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Scheduling Memory Refresh Operations Including Power States
- Publication number 20130138878
- Publication date May 30, 2013
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH LATENC...
- Publication number 20130117513
- Publication date May 9, 2013
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Support a Full Asynchronous Interface within a Memory Hub...
- Publication number 20090193200
- Publication date Jul 30, 2009
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Increase the Overall Bandwidth of a Memory Channel By All...
- Publication number 20090193201
- Publication date Jul 30, 2009
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Reduce Latency by Running a Memory Channel Frequency Full...
- Publication number 20090193203
- Publication date Jul 30, 2009
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Enable a Memory Hub Device to Manage Thermal Conditions a...
- Publication number 20090190427
- Publication date Jul 30, 2009
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Provide Memory System Power Reduction Without Reducing Ov...
- Publication number 20090190429
- Publication date Jul 30, 2009
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT VIA DIMM READ OPERATION LIMITER
- Publication number 20080320323
- Publication date Dec 25, 2008
- International Business Machines Corporation
- Mark Andrew Brittain
- G11 - INFORMATION STORAGE
Information Patent Application
DOUBLE DRAM BIT STEERING FOR MULTIPLE ERROR CORRECTIONS
- Publication number 20080294950
- Publication date Nov 27, 2008
- International Business Machines Corporation
- Luiz Carlos Alves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WRAP TEST MODE USING FUNCTIONAL READ/WRITE BUFFERS
- Publication number 20080126911
- Publication date May 29, 2008
- Mark A. Brittain
- G01 - MEASURING TESTING
Information Patent Application
EXECUTING BACKGROUND WRITES TO IDLE DIMMS
- Publication number 20080091905
- Publication date Apr 17, 2008
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING READS FOR EARLY PROCESSING IN A CASCADED MEMORY SUBSYSTEM...
- Publication number 20080091906
- Publication date Apr 17, 2008
- Mark Andrew Brittain
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Method and apparatus for queuing memory access commands in a memory...
- Publication number 20080091881
- Publication date Apr 17, 2008
- IBM Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for using bit errors from memory to alter memory...
- Publication number 20080072116
- Publication date Mar 20, 2008
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MEMORY MODULE POWER MANAGEMENT
- Publication number 20080040563
- Publication date Feb 14, 2008
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Streaming reads for early processing in a cascaded memory subsystem...
- Publication number 20060179262
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Single burst completion of multiple writes at buffered DIMMs
- Publication number 20060179183
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable bank/timer address folding in memory devices
- Publication number 20060179206
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic power management via DIMM read operation limiter
- Publication number 20060179334
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Executing background writes to idle DIMMs
- Publication number 20060179213
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Mark Andrew Brittain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Double DRAM bit steering for multiple error corrections
- Publication number 20060179362
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Luiz Carlos Alves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power management via DIMM read operation limiter
- Publication number 20060179333
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Mark Andrew Brittain
- G11 - INFORMATION STORAGE
Information Patent Application
Method for identification and removal of non-timing critical wire r...
- Publication number 20040199884
- Publication date Oct 7, 2004
- International Business Machines Corporation
- Mark A. Brittain
- G06 - COMPUTING CALCULATING COUNTING

Mark Andrew BRITTAIN

Person

Patents Grantslast 30 patents

Apparatus and method for controlling access to a memory device

Memory queue handling techniques for reducing impact of high-latenc...

Memory reorder queue biasing preceding high latency operations

Memory reorder queue biasing preceding high latency operations

Method for scheduling memory refresh operations including power states

Apparatus for scheduling memory refresh operations including power...

Power management via DIMM read operation limiter

Streaming reads for early processing in a cascaded memory subsystem...

System to provide memory system power reduction without reducing ov...

System to enable a memory hub device to manage thermal conditions a...

System to reduce latency by running a memory channel frequency full...

System to support a full asynchronous interface within a memory hub...

System to increase the overall bandwidth of a memory channel by all...

Double DRAM bit steering for multiple error corrections

Using bit errors from memory to alter memory command stream

Executing background writes to idle DIMMS

Systems and methods for memory module power management

Memory wrap test mode using functional read/write buffers

Double DRAM bit steering for multiple error corrections

Programmable bank/timer address folding in memory devices

Memory queue with supplemental locations for consecutive addresses

Power management via DIMM read operation limiter

Dynamic power management via DIMM read operation limiter

Executing background writes to idle DIMMs

Streaming reads for early processing in a cascaded memory subsystem...

Method for identification and removal of non-timing critical wire r...

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR CONTROLLING ACCESS TO A MEMORY DEVICE

Memory Reorder Queue Biasing Preceding High Latency Operations

MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH-LATENC...

MEMORY RECORDER QUEUE BIASING PRECEDING HIGH LATENCY OPERATIONS

Method for Scheduling Memory Refresh Operations Including Power States

Method for Scheduling Memory Refresh Operations Including Power States

MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH LATENC...

System to Support a Full Asynchronous Interface within a Memory Hub...

System to Increase the Overall Bandwidth of a Memory Channel By All...

System to Reduce Latency by Running a Memory Channel Frequency Full...

System to Enable a Memory Hub Device to Manage Thermal Conditions a...

System to Provide Memory System Power Reduction Without Reducing Ov...

POWER MANAGEMENT VIA DIMM READ OPERATION LIMITER

DOUBLE DRAM BIT STEERING FOR MULTIPLE ERROR CORRECTIONS

MEMORY WRAP TEST MODE USING FUNCTIONAL READ/WRITE BUFFERS

EXECUTING BACKGROUND WRITES TO IDLE DIMMS

STREAMING READS FOR EARLY PROCESSING IN A CASCADED MEMORY SUBSYSTEM...

Method and apparatus for queuing memory access commands in a memory...

System and method for using bit errors from memory to alter memory...

SYSTEMS AND METHODS FOR MEMORY MODULE POWER MANAGEMENT

Streaming reads for early processing in a cascaded memory subsystem...

Single burst completion of multiple writes at buffered DIMMs

Programmable bank/timer address folding in memory devices

Dynamic power management via DIMM read operation limiter

Executing background writes to idle DIMMs

Double DRAM bit steering for multiple error corrections

Power management via DIMM read operation limiter

Method for identification and removal of non-timing critical wire r...