Mark B. Ritter

Person

Sherman, CT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Optically multiplexed quantum control interface
- Patent number 12,026,584
- Issue date Jul 2, 2024
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quantum device with modular quantum building blocks
- Patent number 11,812,673
- Issue date Nov 7, 2023
- International Business Machines Corporation
- Salvatore Bernardo Olivadese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems of neuron leaky integrate and fire circuits
- Patent number 11,308,390
- Issue date Apr 19, 2022
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optically multiplexed quantum control
- Patent number 11,201,686
- Issue date Dec 14, 2021
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quantum device with modular quantum building blocks
- Patent number 10,971,672
- Issue date Apr 6, 2021
- International Business Machines Corporation
- Salvatore Bernardo Olivadese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Current mirror scheme for an integrating neuron circuit
- Patent number 10,671,911
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems of neuron leaky integrate and fire circuits
- Patent number 10,643,125
- Issue date May 5, 2020
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single-flux-quantum probabilistic digitizer
- Patent number 9,793,913
- Issue date Oct 17, 2017
- International Business Machines Corporation
- John F. Bulzacchelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single-flux-quantum probabilistic digitizer
- Patent number 9,614,532
- Issue date Apr 4, 2017
- International Business Machines Corporation
- John F. Bulzacchelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resistive random access memory devices with extremely reactive cont...
- Patent number 9,203,022
- Issue date Dec 1, 2015
- GLOBALFOUNDRIES Inc.
- Marinus J. Hopstaken
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Soft error protection in individual memory devices
- Patent number 8,949,685
- Issue date Feb 3, 2015
- International Business Machines Corporation
- Douglas J. Joseph
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic synapses from stochastic binary memory devices
- Patent number 8,832,010
- Issue date Sep 9, 2014
- International Business Machines Corporation
- Bipin Rajendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic synapses from stochastic binary memory devices
- Patent number 8,832,011
- Issue date Sep 9, 2014
- International Business Machines Corporation
- Bipin Rajendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for address-event-representation network simulation
- Patent number 8,429,107
- Issue date Apr 23, 2013
- International Business Machines Corporation
- Monty M. Denneau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for analog frequency clocking in processor cores
- Patent number 8,161,314
- Issue date Apr 17, 2012
- International Business Machines Corporation
- Lawrence Jacobowitz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Three-dimensional cascaded power distribution in a semiconductor de...
- Patent number 8,053,819
- Issue date Nov 8, 2011
- International Business Machines Corporation
- Kerry Bernstein
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of optimizing performance of multi-core chips and correspond...
- Patent number 7,917,785
- Issue date Mar 29, 2011
- International Business Machines Corporation
- Lawrence Jacobowitz
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and system for digital frequency clocking in processor cores
- Patent number 7,917,799
- Issue date Mar 29, 2011
- International Business Machines Corporation
- Lawrence Jacobowitz
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Wafer level I/O test, repair and/or customization enabled by I/O layer
- Patent number 7,913,202
- Issue date Mar 22, 2011
- International Business Machines Corporation
- Kerry Bernstein
- G11 - INFORMATION STORAGE
Information Patent Grant
Impedance matching circuit with simultaneous shielding of parasitic...
- Patent number 7,720,386
- Issue date May 18, 2010
- International Business Machines Corporation
- Daniel M. Kuchta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Soft error protection in individual memory devices
- Patent number 7,721,182
- Issue date May 18, 2010
- International Business Machines Corporation
- Douglas J. Joseph
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer level I/O test and repair enabled by I/O layer
- Patent number 7,521,950
- Issue date Apr 21, 2009
- International Business Machines Corporation
- Kerry Bernstein
- G11 - INFORMATION STORAGE
Information Patent Grant
Impedance matching circuit with simultaneous shielding of parasitic...
- Patent number 7,509,053
- Issue date Mar 24, 2009
- International Business Machines Corporation
- Daniel M. Kuchta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Impedance matching circuit with simultaneous shielding of parasitic...
- Patent number 7,412,172
- Issue date Aug 12, 2008
- International Business Machines Corporation
- Daniel M. Kuchta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Three-dimensional cascaded power distribution in a semiconductor de...
- Patent number 7,402,854
- Issue date Jul 22, 2008
- International Business Machines Corporation
- Kerry Bernstein
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-cost radio frequency (RF) link for point-to-point data transfer
- Patent number 6,754,259
- Issue date Jun 22, 2004
- International Business Machines Corporation
- Brian Paul Gaucher
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-protocol agile framer
- Patent number 6,654,383
- Issue date Nov 25, 2003
- International Business Machines Corporation
- Charles Louis Haymes
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Silicon-on-insulator (SOI) trench photodiode
- Patent number 6,538,299
- Issue date Mar 25, 2003
- International Business Machines Corporation
- Young H. Kwark
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and circuit for automatically correcting offset voltage
- Patent number 6,507,241
- Issue date Jan 14, 2003
- International Business Machines Corporation
- Mark B. Ritter
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit-compatible photo detector device and fabrication...
- Patent number 5,994,162
- Issue date Nov 30, 1999
- International Business Machines Corporation
- Joachim Norbert Burghartz
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
IMPROVING THE BANDWIDTH OF CLASSICAL NETWORKS USING QUANTUM NETWORKS
- Publication number 20240322915
- Publication date Sep 26, 2024
- International Business Machines Corporation
- Dinesh C. Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING QUANTUM NETWORKS TO DISTRIBUTE CONFIGURATIONS IN A DISTRIBUTE...
- Publication number 20240320531
- Publication date Sep 26, 2024
- International Business Machines Corporation
- Utpal Mangla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optically Multiplexed Quantum Control Interface
- Publication number 20220156619
- Publication date May 19, 2022
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUANTUM DEVICE WITH MODULAR QUANTUM BUILDING BLOCKS
- Publication number 20210151657
- Publication date May 20, 2021
- International Business Machines Corporation
- Salvatore Bernardo Olivadese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUANTUM DEVICE WITH MODULAR QUANTUM BUILDING BLOCKS
- Publication number 20200035902
- Publication date Jan 30, 2020
- International Business Machines Corporation
- Salvatore Bernardo Olivadese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS
- Publication number 20200026994
- Publication date Jan 23, 2020
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS
- Publication number 20170255860
- Publication date Sep 7, 2017
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Current Mirror Scheme for An Integrating Neuron Circuit
- Publication number 20170243108
- Publication date Aug 24, 2017
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE-FLUX-QUANTUM PROBABILISTIC DIGITIZER
- Publication number 20170179973
- Publication date Jun 22, 2017
- International Business Machines Corporation
- John F. Bulzacchelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PULSE GENERATOR WITH SWITCHED CAPACITORS
- Publication number 20170047911
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PULSE GENERATOR WITH SWITCHED CAPACITORS
- Publication number 20170047914
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTIVE RANDOM ACCESS MEMORY DEVICES WITH EXTREMELY REACTIVE CONT...
- Publication number 20150243888
- Publication date Aug 27, 2015
- International Business Machines Corporation
- Marinus J. Hopstaken
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTIVE RANDOM ACCESS MEMORY DEVICES WITH EXTREMELY REACTIVE CONT...
- Publication number 20150028279
- Publication date Jan 29, 2015
- International Business Machines Corporation
- Marinus J. Hopstaken
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES
- Publication number 20130173515
- Publication date Jul 4, 2013
- International Business Machines Corporation
- Bipin Rajendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES
- Publication number 20130173516
- Publication date Jul 4, 2013
- International Business Machines Corporation
- Bipin Rajendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR ADDRESS-EVENT-REPRESENTATION NETWORK SIMULATION
- Publication number 20110106741
- Publication date May 5, 2011
- International Business Machines Corporation
- Monty M. Denneau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Soft Error Protection in Individual Memory Devices
- Publication number 20100146369
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Douglas J. Joseph
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPEDANCE MATCHING CIRCUIT WITH SIMULTANEOUS SHIELDING OF PARASITIC...
- Publication number 20090034980
- Publication date Feb 5, 2009
- DANIEL M. KUCHTA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD OF OPTIMIZING PERFORMANCE OF MULTI-CORE CHIPS AND CORRESPOND...
- Publication number 20080282074
- Publication date Nov 13, 2008
- Lawrence Jacobowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR ANALOG FREQUENCY CLOCKING IN PROCESSOR CORES
- Publication number 20080256381
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Lawrence Jacobowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR DIGITAL FREQUENCY CLOCKING IN PROCESSOR CORES
- Publication number 20080256382
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Lawrence Jacobowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three-Dimensional Cascaded Power Distribution in a Semiconductor De...
- Publication number 20080203445
- Publication date Aug 28, 2008
- International Business Machines Corporation
- Kerry Bernstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING...
- Publication number 20080165521
- Publication date Jul 10, 2008
- KERRY BERNSTEIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer
- Publication number 20080068039
- Publication date Mar 20, 2008
- Kerry Bernstein
- G11 - INFORMATION STORAGE
Information Patent Application
IMPEDANCE MATCHING CIRCUIT WITH SIMULTANEOUS SHIELDING OF PARASITIC...
- Publication number 20080037993
- Publication date Feb 14, 2008
- Daniel M. Kuchta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Three-dimensional cascaded power distribution in a semiconductor de...
- Publication number 20080023731
- Publication date Jan 31, 2008
- International Business Machines Corporation
- Kerry Bernstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WAFER LEVEL I/O TEST AND REPAIR ENABLED BY I/O LAYER
- Publication number 20070081410
- Publication date Apr 12, 2007
- International Business Machines Corporation
- Kerry Bernstein
- G11 - INFORMATION STORAGE
Information Patent Application
Soft error protection in individual memory devices
- Publication number 20060282745
- Publication date Dec 14, 2006
- International Business Machines Corporation
- Douglas J. Joseph
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Impedance matching circuit with simultaneous shielding of parasitic...
- Publication number 20050123302
- Publication date Jun 9, 2005
- Daniel M. Kuchta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multi-protocol agile framer
- Publication number 20020191640
- Publication date Dec 19, 2002
- International Business Machines Corporation
- Charles Louis Haymes
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Mark B. Ritter

Person

Patents Grantslast 30 patents

Optically multiplexed quantum control interface

Quantum device with modular quantum building blocks

Methods and systems of neuron leaky integrate and fire circuits

Optically multiplexed quantum control

Quantum device with modular quantum building blocks

Current mirror scheme for an integrating neuron circuit

Methods and systems of neuron leaky integrate and fire circuits

Single-flux-quantum probabilistic digitizer

Single-flux-quantum probabilistic digitizer

Resistive random access memory devices with extremely reactive cont...

Soft error protection in individual memory devices

Electronic synapses from stochastic binary memory devices

Electronic synapses from stochastic binary memory devices

System for address-event-representation network simulation

Method and system for analog frequency clocking in processor cores

Three-dimensional cascaded power distribution in a semiconductor de...

Method of optimizing performance of multi-core chips and correspond...

Method and system for digital frequency clocking in processor cores

Wafer level I/O test, repair and/or customization enabled by I/O layer

Impedance matching circuit with simultaneous shielding of parasitic...

Soft error protection in individual memory devices

Wafer level I/O test and repair enabled by I/O layer

Impedance matching circuit with simultaneous shielding of parasitic...

Impedance matching circuit with simultaneous shielding of parasitic...

Three-dimensional cascaded power distribution in a semiconductor de...

Low-cost radio frequency (RF) link for point-to-point data transfer

Multi-protocol agile framer

Silicon-on-insulator (SOI) trench photodiode

Method and circuit for automatically correcting offset voltage

Integrated circuit-compatible photo detector device and fabrication...

Patents Applicationslast 30 patents

IMPROVING THE BANDWIDTH OF CLASSICAL NETWORKS USING QUANTUM NETWORKS

USING QUANTUM NETWORKS TO DISTRIBUTE CONFIGURATIONS IN A DISTRIBUTE...

Optically Multiplexed Quantum Control Interface

QUANTUM DEVICE WITH MODULAR QUANTUM BUILDING BLOCKS

QUANTUM DEVICE WITH MODULAR QUANTUM BUILDING BLOCKS

METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS

METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS

Current Mirror Scheme for An Integrating Neuron Circuit

SINGLE-FLUX-QUANTUM PROBABILISTIC DIGITIZER

PULSE GENERATOR WITH SWITCHED CAPACITORS

PULSE GENERATOR WITH SWITCHED CAPACITORS

RESISTIVE RANDOM ACCESS MEMORY DEVICES WITH EXTREMELY REACTIVE CONT...

RESISTIVE RANDOM ACCESS MEMORY DEVICES WITH EXTREMELY REACTIVE CONT...

ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES

ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES

SYSTEM FOR ADDRESS-EVENT-REPRESENTATION NETWORK SIMULATION

Soft Error Protection in Individual Memory Devices

IMPEDANCE MATCHING CIRCUIT WITH SIMULTANEOUS SHIELDING OF PARASITIC...

METHOD OF OPTIMIZING PERFORMANCE OF MULTI-CORE CHIPS AND CORRESPOND...

METHOD AND SYSTEM FOR ANALOG FREQUENCY CLOCKING IN PROCESSOR CORES

METHOD AND SYSTEM FOR DIGITAL FREQUENCY CLOCKING IN PROCESSOR CORES

Three-Dimensional Cascaded Power Distribution in a Semiconductor De...

THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING...

Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer

IMPEDANCE MATCHING CIRCUIT WITH SIMULTANEOUS SHIELDING OF PARASITIC...

Three-dimensional cascaded power distribution in a semiconductor de...

WAFER LEVEL I/O TEST AND REPAIR ENABLED BY I/O LAYER

Soft error protection in individual memory devices

Impedance matching circuit with simultaneous shielding of parasitic...

Multi-protocol agile framer