Mark Baumann

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor chip layout
- Patent number 8,901,747
- Issue date Dec 2, 2014
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip layout with staggered Tx and Tx data lines
- Patent number 8,890,332
- Issue date Nov 18, 2014
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with segregated Tx and Rx data channels
- Patent number 8,368,217
- Issue date Feb 5, 2013
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Content addressable memory (CAM) devices having soft priority resol...
- Patent number 7,669,005
- Issue date Feb 23, 2010
- NetLogic Microsystems, Inc.
- Kee Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory array having flexible priority support
- Patent number 6,996,662
- Issue date Feb 7, 2006
- Integrated Device Technology, Inc.
- Michael J. Miller
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory (CAM) devices having error detection and...
- Patent number 6,879,504
- Issue date Apr 12, 2005
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory (CAM) devices that utilize multi-port CA...
- Patent number 6,781,857
- Issue date Aug 24, 2004
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Network translation circuit and method using a segmentable content...
- Patent number 6,732,227
- Issue date May 4, 2004
- Integrated Device Technology, Inc.
- Mark Baumann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Separate byte control on fully synchronous pipelined SRAM
- Patent number 6,591,354
- Issue date Jul 8, 2003
- Integrated Device Technology, Inc.
- John R. Mick
- G11 - INFORMATION STORAGE
Information Patent Grant
Quad data rate RAM
- Patent number 6,381,684
- Issue date Apr 30, 2002
- Integrated Device Technology, Inc.
- Stanley A. Hronik
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-ported memory architecture using single-ported RAM
- Patent number 6,212,607
- Issue date Apr 3, 2001
- Integrated Device Technology, Inc.
- Michael Miller
- G11 - INFORMATION STORAGE
Information Patent Grant
Separate byte control on fully synchronous pipelined SRAM
- Patent number 6,115,320
- Issue date Sep 5, 2000
- Integrated Device Technology, Inc.
- John R. Mick
- G11 - INFORMATION STORAGE
Information Patent Grant
Semaphore enhancement to allow bank selection of a shared resource...
- Patent number 6,108,756
- Issue date Aug 22, 2000
- Integrated Device Technology, Inc.
- Michael Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separate byte control on fully synchronous pipelined SRAM
- Patent number 6,081,478
- Issue date Jun 27, 2000
- Integrated Device Technology, Inc.
- John R. Mick
- G11 - INFORMATION STORAGE
Information Patent Grant
Mail-box design for non-blocking communication across ports of a mu...
- Patent number 5,751,638
- Issue date May 12, 1998
- Integrated Device Technology, Inc.
- John Mick
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS
- Publication number 20130313723
- Publication date Nov 28, 2013
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS
- Publication number 20120267769
- Publication date Oct 25, 2012
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VLSI Package for High Performance Integrated Circuit
- Publication number 20120068339
- Publication date Mar 22, 2012
- MoSys, Inc.
- Michael J. Miller
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor Chip Layout
- Publication number 20120025397
- Publication date Feb 2, 2012
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Content addressable memory array having flexible priority support
- Publication number 20030005146
- Publication date Jan 2, 2003
- Integrated Device Technology, Inc.
- Michael J. Miller
- G11 - INFORMATION STORAGE

Mark Baumann

Person

Patents Grantslast 30 patents

Semiconductor chip layout

Semiconductor chip layout with staggered Tx and Tx data lines

Integrated circuit package with segregated Tx and Rx data channels

Content addressable memory (CAM) devices having soft priority resol...

Content addressable memory array having flexible priority support

Content addressable memory (CAM) devices having error detection and...

Content addressable memory (CAM) devices that utilize multi-port CA...

Network translation circuit and method using a segmentable content...

Separate byte control on fully synchronous pipelined SRAM

Quad data rate RAM

Multi-ported memory architecture using single-ported RAM

Separate byte control on fully synchronous pipelined SRAM

Semaphore enhancement to allow bank selection of a shared resource...

Separate byte control on fully synchronous pipelined SRAM

Mail-box design for non-blocking communication across ports of a mu...

Patents Applicationslast 30 patents

SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS

INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS

VLSI Package for High Performance Integrated Circuit

Semiconductor Chip Layout

Content addressable memory array having flexible priority support