Mark David Jacunski

Person

Collhester, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Latching current sensing amplifier for memory array
- Patent number 10,535,379
- Issue date Jan 14, 2020
- GLOBALFOUNDRIES Inc.
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip reliability monitor and method
- Patent number 10,429,434
- Issue date Oct 1, 2019
- GLOBALFOUNDRIES Inc.
- John A. Fifield
- G01 - MEASURING TESTING
Information Patent Grant
Static random access memory (SRAM) write assist circuit with improv...
- Patent number 10,020,047
- Issue date Jul 10, 2018
- GLOBALFOUNDRIES Inc.
- Eric D. Hunt-Schroeder
- G11 - INFORMATION STORAGE
Information Patent Grant
Double-sided segmented line architecture in 3D integration
- Patent number 9,870,979
- Issue date Jan 16, 2018
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latching current sensing amplifier for memory array
- Patent number 9,779,783
- Issue date Oct 3, 2017
- GLOBALFOUNDRIES Inc.
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Double-sided segmented line architecture in 3D integration
- Patent number 9,559,040
- Issue date Jan 31, 2017
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Signal margin centering for single-ended eDRAM sense amplifier
- Patent number 9,093,175
- Issue date Jul 28, 2015
- International Business Machines Corporation
- John E. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with on and off-state wordline voltages having differe...
- Patent number 8,902,679
- Issue date Dec 2, 2014
- International Business Machines Corporation
- John A. Fifield
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-bank random access memory structure with global and local sig...
- Patent number 8,649,239
- Issue date Feb 11, 2014
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Timer lockout circuit for synchronous applications
- Patent number 7,221,601
- Issue date May 22, 2007
- International Business Machines Corporation
- Mark D Jacunski
- G11 - INFORMATION STORAGE
Information Patent Grant
Command multiplier for built-in-self-test
- Patent number 7,194,670
- Issue date Mar 20, 2007
- International Business Machines Corp.
- Jonathan R. Fales
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and structure for enabling a redundancy allocation during a...
- Patent number 7,085,180
- Issue date Aug 1, 2006
- International Business Machines Corporation
- Gregory J. Fredeman
- G11 - INFORMATION STORAGE
Information Patent Grant
Timer lockout circuit for synchronous applications
- Patent number 7,068,564
- Issue date Jun 27, 2006
- International Business Machines Corporation
- Mark D Jacunski
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline on and off voltage compensation circuit based on the array...
- Patent number 6,693,843
- Issue date Feb 17, 2004
- Infineon Technologies AG
- Thomas M. Maffitt
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM word line voltage control to insure full cell writeback level
- Patent number 6,580,650
- Issue date Jun 17, 2003
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-charge circuit and method for memory devices with shared sense...
- Patent number 6,580,655
- Issue date Jun 17, 2003
- International Business Machines Corporation
- Mark D. Jacunski
- G11 - INFORMATION STORAGE
Information Patent Grant
Oxide tracking voltage reference
- Patent number 6,522,154
- Issue date Feb 18, 2003
- International Business Machines Corporation
- John Atkinson Fifield
- G01 - MEASURING TESTING
Information Patent Grant
Isolated well ESD device
- Patent number 6,399,990
- Issue date Jun 4, 2002
- International Business Machines Corporation
- Ciaran J. Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable delay element and synchronous DRAM using the same
- Patent number 6,400,202
- Issue date Jun 4, 2002
- International Business Machines Corporation
- John A. Fifield
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable delay element and synchronous DRAM using the same
- Patent number 6,348,827
- Issue date Feb 19, 2002
- International Business Machines Corporation
- John A. Fifield
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ON-CHIP RELIABILITY MONITOR AND METHOD
- Publication number 20190265293
- Publication date Aug 29, 2019
- John A. Fifield
- G01 - MEASURING TESTING
Information Patent Application
LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY
- Publication number 20170365302
- Publication date Dec 21, 2017
- GLOBALFOUNDRIES INC.
- Darren L. ANAND
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH IMPROV...
- Publication number 20170270999
- Publication date Sep 21, 2017
- GLOBALFOUNDRIES INC.
- Eric D. HUNT-SCHROEDER
- G11 - INFORMATION STORAGE
Information Patent Application
LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY
- Publication number 20160372164
- Publication date Dec 22, 2016
- International Business Machines Corporation
- Darren L. ANAND
- G11 - INFORMATION STORAGE
Information Patent Application
DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION
- Publication number 20150364401
- Publication date Dec 17, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION
- Publication number 20150187642
- Publication date Jul 2, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIGNAL MARGIN CENTERING FOR SINGLE-ENDED eDRAM SENSE AMPLIFIER
- Publication number 20140293715
- Publication date Oct 2, 2014
- International Business Machines Corporation
- JOHN E. BARTH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERE...
- Publication number 20140003164
- Publication date Jan 2, 2014
- International Business Machines Corporation
- John A. Fifield
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIG...
- Publication number 20130315022
- Publication date Nov 28, 2013
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
Morphing Memory Architecture
- Publication number 20120036315
- Publication date Feb 9, 2012
- International Business Machines Corporation
- William R. Reohr
- G11 - INFORMATION STORAGE
Information Patent Application
Timer lockout circuit for synchronous applications
- Publication number 20060152994
- Publication date Jul 13, 2006
- Mark D. Jacunski
- G11 - INFORMATION STORAGE
Information Patent Application
A Command Multiplier for Built-In-Self-Test
- Publication number 20050193253
- Publication date Sep 1, 2005
- International Business Machines Corporation
- Jonathan R. Fales
- G11 - INFORMATION STORAGE
Information Patent Application
Method and structure for enabling a redundancy allocation during a...
- Publication number 20050180230
- Publication date Aug 18, 2005
- Gregory J. Fredeman
- G11 - INFORMATION STORAGE
Information Patent Application
Timer lockout circuit for synchronous applications
- Publication number 20040264289
- Publication date Dec 30, 2004
- International Business Machines Corporation
- Mark D Jacunski
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-charge circuit and method for memory devices with shared sense...
- Publication number 20030043666
- Publication date Mar 6, 2003
- International Business Machines Corporation
- Mark D. Jacunski
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM word line voltage control to insure full cell writeback level
- Publication number 20020159301
- Publication date Oct 31, 2002
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
Oxide tracking voltage reference
- Publication number 20020130672
- Publication date Sep 19, 2002
- International Business Machines Corporation
- John Atkinson Fifield
- G01 - MEASURING TESTING
Information Patent Application
Programmable delay element and synchronous dram using the same
- Publication number 20020030524
- Publication date Mar 14, 2002
- John A. Fifield
- G11 - INFORMATION STORAGE

Mark David Jacunski

Person

Patents Grantslast 30 patents

Latching current sensing amplifier for memory array

On-chip reliability monitor and method

Static random access memory (SRAM) write assist circuit with improv...

Double-sided segmented line architecture in 3D integration

Latching current sensing amplifier for memory array

Double-sided segmented line architecture in 3D integration

Signal margin centering for single-ended eDRAM sense amplifier

Memory array with on and off-state wordline voltages having differe...

Multi-bank random access memory structure with global and local sig...

Timer lockout circuit for synchronous applications

Command multiplier for built-in-self-test

Method and structure for enabling a redundancy allocation during a...

Timer lockout circuit for synchronous applications

Wordline on and off voltage compensation circuit based on the array...

DRAM word line voltage control to insure full cell writeback level

Pre-charge circuit and method for memory devices with shared sense...

Oxide tracking voltage reference

Isolated well ESD device

Programmable delay element and synchronous DRAM using the same

Programmable delay element and synchronous DRAM using the same

Patents Applicationslast 30 patents

ON-CHIP RELIABILITY MONITOR AND METHOD

LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY

STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH IMPROV...

LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY

DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION

DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION

SIGNAL MARGIN CENTERING FOR SINGLE-ENDED eDRAM SENSE AMPLIFIER

MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERE...

MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIG...

Morphing Memory Architecture

Timer lockout circuit for synchronous applications

A Command Multiplier for Built-In-Self-Test

Method and structure for enabling a redundancy allocation during a...

Timer lockout circuit for synchronous applications

Pre-charge circuit and method for memory devices with shared sense...

DRAM word line voltage control to insure full cell writeback level

Oxide tracking voltage reference

Programmable delay element and synchronous dram using the same