Mark Debbage

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reliable transport architecture
- Patent number 12,212,502
- Issue date Jan 28, 2025
- Intel Corporation
- Mark Debbage
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Direct memory writes by network interface of a graphics processing...
- Patent number 12,190,405
- Issue date Jan 7, 2025
- Intel Corporation
- Todd Rimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus, and method for streaming input/output data
- Patent number 12,177,277
- Issue date Dec 24, 2024
- Intel Corporation
- Lokpraveen Mosur
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scalable protocol-agnostic reliable transport
- Patent number 12,137,001
- Issue date Nov 5, 2024
- Intel Corporation
- Mark Debbage
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for managing a latency-efficient pipeline through a ne...
- Patent number 11,467,885
- Issue date Oct 11, 2022
- Intel Corporation
- Ronen Hyatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sending packets using optimized PIO write sequences without SFENCES
- Patent number 10,073,796
- Issue date Sep 11, 2018
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliable out-of order end-to-end protocol with robust window state...
- Patent number 10,044,626
- Issue date Aug 7, 2018
- Intel Corporation
- Keith Underwood
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System, method and apparatus for improving the performance of colle...
- Patent number 10,015,056
- Issue date Jul 3, 2018
- Intel Corporation
- Michael Heinz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimized credit return mechanism for packet sends
- Patent number 9,984,020
- Issue date May 29, 2018
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized credit return mechanism for packet sends
- Patent number 9,792,235
- Issue date Oct 17, 2017
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sending packets using optimized PIO write sequences without sfences...
- Patent number 9,785,359
- Issue date Oct 10, 2017
- Intel Corporation
- Yatin Mutha
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Sending packets using optimized PIO write sequences without sfences
- Patent number 9,734,077
- Issue date Aug 15, 2017
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sending packets using optimized PIO write sequences without sfences
- Patent number 9,588,899
- Issue date Mar 7, 2017
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized credit return mechanism for packet sends
- Patent number 9,477,631
- Issue date Oct 25, 2016
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sending packets using optimized PIO write sequences without SFENCEs
- Patent number 9,460,019
- Issue date Oct 4, 2016
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method and apparatus for improving the performance of colle...
- Patent number 9,391,845
- Issue date Jul 12, 2016
- Intel Corporation
- Michael Heinz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimizing hardware TLB reload performance in a highly-threaded pro...
- Patent number 7,543,132
- Issue date Jun 2, 2009
- Sun Microsystems, Inc.
- Greg F. Grohoski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PACKET HEADER OPTIMIZATION IN ETHERNET INTERNET PROTOCOL NETWORKS
- Publication number 20230412712
- Publication date Dec 21, 2023
- Intel Corporation
- Nayan Suthar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIRECT MEMORY WRITES BY NETWORK INTERFACE OF A GRAPHICS PROCESSING...
- Publication number 20220351326
- Publication date Nov 3, 2022
- Intel Corporation
- Todd RIMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATIONS FOR WORKLOADS
- Publication number 20220138021
- Publication date May 5, 2022
- Intel Corporation
- Todd RIMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR STORAGE OF RECEIVED MESSAGES
- Publication number 20220124046
- Publication date Apr 21, 2022
- Intel Corporation
- Mark DEBBAGE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SWITCH-ORIGINATED CONGESTION MESSAGES
- Publication number 20220124035
- Publication date Apr 21, 2022
- Intel Corporation
- Junggun LEE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PACKET FORMAT ADJUSTMENT TECHNOLOGIES
- Publication number 20220116325
- Publication date Apr 14, 2022
- Intel Corporation
- Bruce G. WARREN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SCALABLE PROTOCOL-AGNOSTIC RELIABLE TRANSPORT
- Publication number 20220085916
- Publication date Mar 17, 2022
- Intel Corporation
- Mark DEBBAGE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM, APPARATUS, AND METHOD FOR STREAMING INPUT/OUTPUT DATA
- Publication number 20210281618
- Publication date Sep 9, 2021
- Intel Corporation
- LOKPRAVEEN MOSUR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RELIABLE TRANSPORT ARCHITECTURE
- Publication number 20210119930
- Publication date Apr 22, 2021
- Intel Corporation
- Mark DEBBAGE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR MANAGING A LATENCY-EFFICIENT PIPELINE THROUGH A NE...
- Publication number 20190068509
- Publication date Feb 28, 2019
- Intel Corporation
- Ronen Hyatt
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS
- Publication number 20180039593
- Publication date Feb 8, 2018
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES...
- Publication number 20170249079
- Publication date Aug 31, 2017
- YATIN MUTHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS
- Publication number 20170235693
- Publication date Aug 17, 2017
- lntel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reliable out-of order end-to-end protocol with robust window state...
- Publication number 20170187637
- Publication date Jun 29, 2017
- Keith D. UNDERWOOD
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES
- Publication number 20170177516
- Publication date Jun 22, 2017
- lntel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES
- Publication number 20170017465
- Publication date Jan 19, 2017
- lntel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES
- Publication number 20160371056
- Publication date Dec 22, 2016
- lntel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD AND APPARATUS FOR IMPROVING THE PERFORMANCE OF COLLE...
- Publication number 20160323150
- Publication date Nov 3, 2016
- lntel Corporation
- Michael Heinz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM, METHOD AND APPARATUS FOR IMPROVING THE PERFORMANCE OF COLLE...
- Publication number 20160087848
- Publication date Mar 24, 2016
- Michael Heinz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES
- Publication number 20150378737
- Publication date Dec 31, 2015
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS
- Publication number 20150378953
- Publication date Dec 31, 2015
- Intel Corporation
- Mark Debbage
- G06 - COMPUTING CALCULATING COUNTING

Mark Debbage

Person

Patents Grantslast 30 patents

Reliable transport architecture

Direct memory writes by network interface of a graphics processing...

System, apparatus, and method for streaming input/output data

Scalable protocol-agnostic reliable transport

Technologies for managing a latency-efficient pipeline through a ne...

Sending packets using optimized PIO write sequences without SFENCES

Reliable out-of order end-to-end protocol with robust window state...

System, method and apparatus for improving the performance of colle...

Optimized credit return mechanism for packet sends

Optimized credit return mechanism for packet sends

Sending packets using optimized PIO write sequences without sfences...

Sending packets using optimized PIO write sequences without sfences

Sending packets using optimized PIO write sequences without sfences

Optimized credit return mechanism for packet sends

Sending packets using optimized PIO write sequences without SFENCEs

System, method and apparatus for improving the performance of colle...

Optimizing hardware TLB reload performance in a highly-threaded pro...

Patents Applicationslast 30 patents

PACKET HEADER OPTIMIZATION IN ETHERNET INTERNET PROTOCOL NETWORKS

DIRECT MEMORY WRITES BY NETWORK INTERFACE OF A GRAPHICS PROCESSING...

COMMUNICATIONS FOR WORKLOADS

SYSTEM FOR STORAGE OF RECEIVED MESSAGES

SWITCH-ORIGINATED CONGESTION MESSAGES

PACKET FORMAT ADJUSTMENT TECHNOLOGIES

SCALABLE PROTOCOL-AGNOSTIC RELIABLE TRANSPORT

SYSTEM, APPARATUS, AND METHOD FOR STREAMING INPUT/OUTPUT DATA

RELIABLE TRANSPORT ARCHITECTURE

TECHNOLOGIES FOR MANAGING A LATENCY-EFFICIENT PIPELINE THROUGH A NE...

OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS

SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES...

OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS

Reliable out-of order end-to-end protocol with robust window state...

SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES

SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES

SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES

SYSTEM, METHOD AND APPARATUS FOR IMPROVING THE PERFORMANCE OF COLLE...

SYSTEM, METHOD AND APPARATUS FOR IMPROVING THE PERFORMANCE OF COLLE...

SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES

OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS