Mark J. Dechene

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for a multi-level reservation station with ins...
- Patent number 10,956,160
- Issue date Mar 23, 2021
- Intel Corporation
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for an early page predictor for a memory pagin...
- Patent number 10,860,319
- Issue date Dec 8, 2020
- Intel Corporation
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting speculative memory optimizations
- Patent number 10,853,078
- Issue date Dec 1, 2020
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods to predict load data values
- Patent number 10,761,844
- Issue date Sep 1, 2020
- Intel Corporation
- Manjunath Shevgoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor prefetch throttling based on short streams
- Patent number 10,379,864
- Issue date Aug 13, 2019
- Intel Corporation
- Chunhui Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting binary translation alias detection in an out-of-order pr...
- Patent number 10,228,956
- Issue date Mar 12, 2019
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for non-blocking register reclamation
- Patent number 9,652,236
- Issue date May 16, 2017
- Intel Corporation
- Srikanth T. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two level re-order buffer
- Patent number 9,495,159
- Issue date Nov 15, 2016
- Intel Corporation
- Mark J. Dechene
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR A ZERO LEVEL CACHE/MEMORY ARCHITECTURE
- Publication number 20240143502
- Publication date May 2, 2024
- Intel Corporation
- Mark DECHENE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS
- Publication number 20240126702
- Publication date Apr 18, 2024
- Intel Corporation
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE PROCESSOR HAVING MULTIPLE MEMORY PREFETCHERS AND MULTIPLE...
- Publication number 20240111679
- Publication date Apr 4, 2024
- Intel Corporation
- Seth Pugsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING MERGED STORE OPERATIONS IN COMPLIANCE WITH STORE ORDERIN...
- Publication number 20240037036
- Publication date Feb 1, 2024
- Intel Corporation
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A MULTI-LEVEL RESERVATION STATION WITH INS...
- Publication number 20200310801
- Publication date Oct 1, 2020
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technology For Providing Memory Atomicity With Low Overhead
- Publication number 20200310798
- Publication date Oct 1, 2020
- Manjunath Shevgoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE PROFILER TO TRACK INSTRUCTION SEQUENCE INFORMATION INCLUDI...
- Publication number 20200210193
- Publication date Jul 2, 2020
- Intel Corporation
- Sangeeta BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SUPPORTING SPECULATIVE MEMORY OPTIMIZATIONS
- Publication number 20200201645
- Publication date Jun 25, 2020
- Intel Corporation
- Vineeth MEKKAT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS TO PREDICT LOAD DATA VALUES
- Publication number 20200004536
- Publication date Jan 2, 2020
- Intel Corporation
- Manjunath SHEVGOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR AN EARLY PAGE PREDICTOR FOR A MEMORY PAGIN...
- Publication number 20190303150
- Publication date Oct 3, 2019
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR PREFETCH THROTTLING BASED ON SHORT STREAMS
- Publication number 20180181402
- Publication date Jun 28, 2018
- Intel Corporation
- CHUNHUI ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING BINARY TRANSLATION ALIAS DETECTION IN AN OUT-OF-ORDER PR...
- Publication number 20180095765
- Publication date Apr 5, 2018
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Non-Blocking Register Reclamation
- Publication number 20150178077
- Publication date Jun 25, 2015
- SRIKANTH T. SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO LEVEL RE-ORDER BUFFER
- Publication number 20150095627
- Publication date Apr 2, 2015
- Mark J. DECHENE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISP...
- Publication number 20140156977
- Publication date Jun 5, 2014
- Mark J. Dechene
- G06 - COMPUTING CALCULATING COUNTING

Mark J. Dechene

Person

Patents Grantslast 30 patents

Method and apparatus for a multi-level reservation station with ins...

Apparatus and method for an early page predictor for a memory pagin...

Method and apparatus for supporting speculative memory optimizations

Systems and methods to predict load data values

Processor prefetch throttling based on short streams

Supporting binary translation alias detection in an out-of-order pr...

Instruction and logic for non-blocking register reclamation

Two level re-order buffer

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR A ZERO LEVEL CACHE/MEMORY ARCHITECTURE

HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS

HARDWARE PROCESSOR HAVING MULTIPLE MEMORY PREFETCHERS AND MULTIPLE...

SCHEDULING MERGED STORE OPERATIONS IN COMPLIANCE WITH STORE ORDERIN...

METHOD AND APPARATUS FOR A MULTI-LEVEL RESERVATION STATION WITH INS...

Technology For Providing Memory Atomicity With Low Overhead

HARDWARE PROFILER TO TRACK INSTRUCTION SEQUENCE INFORMATION INCLUDI...

METHOD AND APPARATUS FOR SUPPORTING SPECULATIVE MEMORY OPTIMIZATIONS

SYSTEMS AND METHODS TO PREDICT LOAD DATA VALUES

APPARATUS AND METHOD FOR AN EARLY PAGE PREDICTOR FOR A MEMORY PAGIN...

PROCESSOR PREFETCH THROTTLING BASED ON SHORT STREAMS

SUPPORTING BINARY TRANSLATION ALIAS DETECTION IN AN OUT-OF-ORDER PR...

Instruction and Logic for Non-Blocking Register Reclamation

TWO LEVEL RE-ORDER BUFFER

ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISP...