Mark Neidengard

Person

Hillsborro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus for autonomous security and functional safety of clock an...
- Patent number 11,461,504
- Issue date Oct 4, 2022
- Intel Corporation
- Nasser Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus to improve lock time of a frequency locked loop
- Patent number 11,211,934
- Issue date Dec 28, 2021
- Intel Corporation
- Praveen Mosalikanti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for autonomous security and functional safety of clock an...
- Patent number 10,824,764
- Issue date Nov 3, 2020
- Intel Corporation
- Nasser Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to perform dynamic frequency scaling while a p...
- Patent number 10,790,838
- Issue date Sep 29, 2020
- Intel Corporation
- Praveen Mosalikanti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus to improve lock time of a frequency locked loop
- Patent number 10,790,832
- Issue date Sep 29, 2020
- Intel Corporation
- Praveen Mosalikanti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bidirectional gray code counter
- Patent number 10,439,617
- Issue date Oct 8, 2019
- Intel Corporation
- Mark L. Neidengard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascaded counter circuit with pipelined reload of variable ratio de...
- Patent number 10,320,395
- Issue date Jun 11, 2019
- Intel Corporation
- Mark Neidengard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus, system, and method for re-synthesizing a clock signal
- Patent number 9,876,491
- Issue date Jan 23, 2018
- Intel Corporation
- Mark Neidengard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generation system with dynamic distribution bypass mode
- Patent number 9,836,078
- Issue date Dec 5, 2017
- Intel Corporation
- Allan Feldman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Quadrature divider
- Patent number 9,698,764
- Issue date Jul 4, 2017
- Intel Corporation
- Mark L. Neidengard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generation system with dynamic distribution bypass mode
- Patent number 9,450,589
- Issue date Sep 20, 2016
- Intel Corporation
- Allan Feldman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid digital pulse width modulation (PWM) based on phases of a sy...
- Patent number 9,438,219
- Issue date Sep 6, 2016
- Intel Corporation
- Harish K. Krishnamurthy
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Apparatus, system, and method for re-synthesizing a clock signal
- Patent number 9,190,991
- Issue date Nov 17, 2015
- Intel Corporation
- Mark Neidengard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency synthesis methods and systems
- Patent number 8,756,451
- Issue date Jun 17, 2014
- Intel Corporation
- Mark L. Neidengard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Missing clock pulse detector
- Patent number 7,679,404
- Issue date Mar 16, 2010
- Intel Corporation
- Mark L. Neidengard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Edge-timing adjustment circuit
- Patent number 7,667,507
- Issue date Feb 23, 2010
- Intel Corporation
- Mark L. Neidengard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Oscillating divider topology
- Patent number 7,405,631
- Issue date Jul 29, 2008
- Intel Corporation
- Mark L. Neidengard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-on detect circuit for use with multiple voltage domains
- Patent number 7,049,865
- Issue date May 23, 2006
- Intel Corporation
- Rachael J. Parker
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS TO IMPROVE LOCK TIME OF A FREQUENCY LOCKED LOOP
- Publication number 20210083678
- Publication date Mar 18, 2021
- Intel Corporation
- Praveen Mosalikanti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AN...
- Publication number 20210049307
- Publication date Feb 18, 2021
- Intel Corporation
- Nasser Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AN...
- Publication number 20200004990
- Publication date Jan 2, 2020
- Intel Corporation
- Nasser Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS TO IMPROVE LOCK TIME OF A FREQUENCY LOCKED LOOP
- Publication number 20190296747
- Publication date Sep 26, 2019
- Intel Corporation
- Praveen Mosalikanti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CASCADED COUNTER CIRCUIT WITH PIPELINED RELOAD OF VARIABLE RATIO DE...
- Publication number 20180212608
- Publication date Jul 26, 2018
- Intel Corporation
- Mark NEIDENGARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIDIRECTIONAL GRAY CODE COUNTER
- Publication number 20170324415
- Publication date Nov 9, 2017
- Intel Corporation
- Mark L. Neidengard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS, SYSTEM, AND METHOD FOR RE-SYNTHESIZING A CLOCK SIGNAL
- Publication number 20160344379
- Publication date Nov 24, 2016
- Intel Corporation
- Mark NEIDENGARD
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK GENERATION SYSTEM WITH DYNAMIC DISTRIBUTION BYPASS MODE
- Publication number 20160327974
- Publication date Nov 10, 2016
- Intel Corporation
- Allan Feldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUADRATURE DIVIDER
- Publication number 20160285436
- Publication date Sep 29, 2016
- Mark L. NEIDENGARD
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS, SYSTEM, AND METHOD FOR RE-SYNTHESIZING A CLOCK SIGNAL
- Publication number 20160056807
- Publication date Feb 25, 2016
- Intel Corporation
- Mark NEIDENGARD
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK GENERATION SYSTEM WITH DYNAMIC DISTRIBUTION BYPASS MODE
- Publication number 20150214959
- Publication date Jul 30, 2015
- Allan Feldman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HYBRID DIGITAL PULSE WIDTH MODULATION (PWM) BASED ON PHASES OF A SY...
- Publication number 20140266136
- Publication date Sep 18, 2014
- Harish K. Krishnamurthy
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
FREQUENCY SYNTHESIS METHODS AND SYSTEMS
- Publication number 20130086410
- Publication date Apr 4, 2013
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EDGE-TIMING ADJUSTMENT CIRCUIT
- Publication number 20090322393
- Publication date Dec 31, 2009
- Mark L. Neidengard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Oscillating divider topology
- Publication number 20080258782
- Publication date Oct 23, 2008
- Mark L. Neidengard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Missing clock pulse detector
- Publication number 20070296467
- Publication date Dec 27, 2007
- Mark L. Neidengard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Duty cycle measurement circuit
- Publication number 20070075753
- Publication date Apr 5, 2007
- Rachael Parker
- G01 - MEASURING TESTING
Information Patent Application
Oscillating divider topology
- Publication number 20060001495
- Publication date Jan 5, 2006
- Mark L. Neidengard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power-on detect circuit for use with multiple voltage domains
- Publication number 20050195000
- Publication date Sep 8, 2005
- Rachael J. Parker
- H03 - BASIC ELECTRONIC CIRCUITRY

Mark Neidengard

Person

Patents Grantslast 30 patents

Apparatus for autonomous security and functional safety of clock an...

Apparatus to improve lock time of a frequency locked loop

Apparatus for autonomous security and functional safety of clock an...

Method and apparatus to perform dynamic frequency scaling while a p...

Apparatus to improve lock time of a frequency locked loop

Bidirectional gray code counter

Cascaded counter circuit with pipelined reload of variable ratio de...

Apparatus, system, and method for re-synthesizing a clock signal

Clock generation system with dynamic distribution bypass mode

Quadrature divider

Clock generation system with dynamic distribution bypass mode

Hybrid digital pulse width modulation (PWM) based on phases of a sy...

Apparatus, system, and method for re-synthesizing a clock signal

Frequency synthesis methods and systems

Missing clock pulse detector

Edge-timing adjustment circuit

Oscillating divider topology

Power-on detect circuit for use with multiple voltage domains

Patents Applicationslast 30 patents

APPARATUS TO IMPROVE LOCK TIME OF A FREQUENCY LOCKED LOOP

APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AN...

APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AN...

APPARATUS TO IMPROVE LOCK TIME OF A FREQUENCY LOCKED LOOP

CASCADED COUNTER CIRCUIT WITH PIPELINED RELOAD OF VARIABLE RATIO DE...

BIDIRECTIONAL GRAY CODE COUNTER

APPARATUS, SYSTEM, AND METHOD FOR RE-SYNTHESIZING A CLOCK SIGNAL

CLOCK GENERATION SYSTEM WITH DYNAMIC DISTRIBUTION BYPASS MODE

QUADRATURE DIVIDER

APPARATUS, SYSTEM, AND METHOD FOR RE-SYNTHESIZING A CLOCK SIGNAL

CLOCK GENERATION SYSTEM WITH DYNAMIC DISTRIBUTION BYPASS MODE

HYBRID DIGITAL PULSE WIDTH MODULATION (PWM) BASED ON PHASES OF A SY...

FREQUENCY SYNTHESIS METHODS AND SYSTEMS

EDGE-TIMING ADJUSTMENT CIRCUIT

Oscillating divider topology

Missing clock pulse detector

Duty cycle measurement circuit

Oscillating divider topology

Power-on detect circuit for use with multiple voltage domains