Mark R. Gardner

Person

Oxnard, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
3D nano sheet method using 2D material integrated with conductive o...
- Patent number 12,176,249
- Issue date Dec 24, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional device with vertical core and bundled wiring
- Patent number 12,170,326
- Issue date Dec 17, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stackable semiconductor device with 2D material layer and methods o...
- Patent number 12,148,668
- Issue date Nov 19, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D memory with conductive dielectric channel integrated with logic...
- Patent number 12,133,387
- Issue date Oct 29, 2024
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
Ultra dense 3D routing for compact 3D designs
- Patent number 12,131,956
- Issue date Oct 29, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making of plurality of 3D vertical logic elements integra...
- Patent number 12,114,480
- Issue date Oct 8, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance 3D vertical transistor device enhancement design
- Patent number 12,087,817
- Issue date Sep 10, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density logic formation using multi-dimensional laser annealing
- Patent number 12,087,640
- Issue date Sep 10, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D high density compact metal first approach for hybrid transistor...
- Patent number 12,068,205
- Issue date Aug 20, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D devices with 3D diffusion breaks and method of forming the same
- Patent number 12,040,236
- Issue date Jul 16, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for threshold voltage tuning through selective deposition of...
- Patent number 12,020,990
- Issue date Jun 25, 2024
- Tokyo Electron Limited
- Jeffrey Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D stacked DRAM with 3D vertical circuit design
- Patent number 12,009,355
- Issue date Jun 11, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to enhance 3D horizontal nanosheets device performance
- Patent number 12,002,809
- Issue date Jun 4, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Precision multi-axis photolithography alignment correction using st...
- Patent number 12,001,147
- Issue date Jun 4, 2024
- Tokyo Electron Limited
- Daniel J. Fulford
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Transistor stack of vertical channel ferroelectric FETs and methods...
- Patent number 11,978,735
- Issue date May 7, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having channel structure with 2D material
- Patent number 11,942,536
- Issue date Mar 26, 2024
- Tokyo Electron Limited
- Robert D. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for designing three dimensional metal lines for enhanced dev...
- Patent number 11,908,747
- Issue date Feb 20, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple nano layer transistor layers with different transistor arc...
- Patent number 11,894,378
- Issue date Feb 6, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High precision 3D metal stacking for a plurality of 3D devices
- Patent number 11,887,897
- Issue date Jan 30, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a plurality of high density logic elements with ad...
- Patent number 11,876,125
- Issue date Jan 16, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making 3D isolation
- Patent number 11,842,919
- Issue date Dec 12, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional device with self-aligned vertical interconnection
- Patent number 11,830,876
- Issue date Nov 28, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-dimensional vertical switching connections for connecting cir...
- Patent number 11,810,854
- Issue date Nov 7, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple planes of transistors with different transistor architectu...
- Patent number 11,777,015
- Issue date Oct 3, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor apparatus having a silicide between two devices
- Patent number 11,776,954
- Issue date Oct 3, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance floating body VFET with dielectric core
- Patent number 11,769,831
- Issue date Sep 26, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density architecture design for 3D logic and 3D memory circuits
- Patent number 11,764,200
- Issue date Sep 19, 2023
- Tokyo Electron Limited
- Mark Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device layout and method using advanced 3D isolation
- Patent number 11,756,836
- Issue date Sep 12, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized stress regions for three-dimension chiplet formation
- Patent number 11,721,551
- Issue date Aug 8, 2023
- Tokyo Electron Limited
- Anton J. Devilliers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making 3D circuits with integrated stacked 3D metal lines...
- Patent number 11,721,582
- Issue date Aug 8, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR TRANSISTOR MEMORY ELEMENT
- Publication number 20240341101
- Publication date Oct 10, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF 3D CANTILEVER CHANNEL FORMATION
- Publication number 20240304701
- Publication date Sep 12, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D U-SHAPED NANOSHEET DEVICE
- Publication number 20240282771
- Publication date Aug 22, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE AND METHOD OF FORMING 3D U-SHAPED NANOSHEET CFET
- Publication number 20240249978
- Publication date Jul 25, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE AND METHOD OF FORMING
- Publication number 20240243182
- Publication date Jul 18, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED NANOSHEET MEMORY ELEMENTS, DEVICES AND METHODS
- Publication number 20240215220
- Publication date Jun 27, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
Information Patent Application
THREE-DIMENSIONAL MULTIPLE LOCATION COMPRESSING BONDED ARM-POISEDON...
- Publication number 20240203797
- Publication date Jun 20, 2024
- TOKYO ELECTRON LIMITED
- Andrew WELOTH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240145595
- Publication date May 2, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
- Publication number 20240145576
- Publication date May 2, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
- Publication number 20240120407
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D NANOSHEET STACK WITH DUAL SELECTIVE CHANNEL REMOVAL OF HIGH MOBI...
- Publication number 20240120336
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE 3D CHANNELS WITH UPSILON NANOSHEETS
- Publication number 20240120375
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING HIGH PERFORMANCE 3D NANO SHEET DEVICES
- Publication number 20240113114
- Publication date Apr 4, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D UFET DEVICES AND METHODS FOR MANUFACTURING THE SAME
- Publication number 20240105777
- Publication date Mar 28, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE 3D COMPACT TRANSISTOR ARCHITECTURE
- Publication number 20240096708
- Publication date Mar 21, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF COMPACT CELL DESIGN FOR LOGIC APPLICATIONS
- Publication number 20240079475
- Publication date Mar 7, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS
- Publication number 20240079452
- Publication date Mar 7, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D HIGH DENSITY DEVICES INTEGRATED WITH SOURCE AND DRAIN RAILS
- Publication number 20240071871
- Publication date Feb 29, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240063261
- Publication date Feb 22, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240063220
- Publication date Feb 22, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY 3D TRANSPORT DEVICE NANO SHEET
- Publication number 20230402505
- Publication date Dec 14, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTO...
- Publication number 20230378364
- Publication date Nov 23, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
- Publication number 20230378366
- Publication date Nov 23, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
- Publication number 20230369505
- Publication date Nov 16, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME
- Publication number 20230352581
- Publication date Nov 2, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC...
- Publication number 20230337435
- Publication date Oct 19, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR STACK OF VERTICAL CHANNEL FERROELECTRIC FETS AND METHODS...
- Publication number 20230335555
- Publication date Oct 19, 2023
- TOKYO ELECTRON LIMITED
- Mark I. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL PLURALITY OF N HORIZONTAL MEMORY CELLS WITH ENHAN...
- Publication number 20230320069
- Publication date Oct 5, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING 3D MEMORY STACKING FORMATION WITH HIGH CIRCUIT DEN...
- Publication number 20230301061
- Publication date Sep 21, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON NANO SHEET THREE-DIMENSIONAL HORIZONTAL MEMORY WITH ALL-ARO...
- Publication number 20230301059
- Publication date Sep 21, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS

Mark R. Gardner

Person

Patents Grantslast 30 patents

3D nano sheet method using 2D material integrated with conductive o...

Three-dimensional device with vertical core and bundled wiring

Stackable semiconductor device with 2D material layer and methods o...

3D memory with conductive dielectric channel integrated with logic...

Ultra dense 3D routing for compact 3D designs

Method of making of plurality of 3D vertical logic elements integra...

High performance 3D vertical transistor device enhancement design

High density logic formation using multi-dimensional laser annealing

3D high density compact metal first approach for hybrid transistor...

3D devices with 3D diffusion breaks and method of forming the same

Method for threshold voltage tuning through selective deposition of...

3D stacked DRAM with 3D vertical circuit design

Method to enhance 3D horizontal nanosheets device performance

Precision multi-axis photolithography alignment correction using st...

Transistor stack of vertical channel ferroelectric FETs and methods...

Semiconductor device having channel structure with 2D material

Method for designing three dimensional metal lines for enhanced dev...

Multiple nano layer transistor layers with different transistor arc...

High precision 3D metal stacking for a plurality of 3D devices

Method of making a plurality of high density logic elements with ad...

Method of making 3D isolation

Three-dimensional device with self-aligned vertical interconnection

Multi-dimensional vertical switching connections for connecting cir...

Multiple planes of transistors with different transistor architectu...

Semiconductor apparatus having a silicide between two devices

High performance floating body VFET with dielectric core

High density architecture design for 3D logic and 3D memory circuits

3D device layout and method using advanced 3D isolation

Localized stress regions for three-dimension chiplet formation

Method of making 3D circuits with integrated stacked 3D metal lines...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE AND METHOD FOR TRANSISTOR MEMORY ELEMENT

METHOD OF 3D CANTILEVER CHANNEL FORMATION

3D U-SHAPED NANOSHEET DEVICE

DEVICE AND METHOD OF FORMING 3D U-SHAPED NANOSHEET CFET

MICROELECTRONIC DEVICE AND METHOD OF FORMING

INTEGRATED NANOSHEET MEMORY ELEMENTS, DEVICES AND METHODS

THREE-DIMENSIONAL MULTIPLE LOCATION COMPRESSING BONDED ARM-POISEDON...

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

3D NANOSHEET STACK WITH DUAL SELECTIVE CHANNEL REMOVAL OF HIGH MOBI...

HIGH PERFORMANCE 3D CHANNELS WITH UPSILON NANOSHEETS

METHODS FOR FORMING HIGH PERFORMANCE 3D NANO SHEET DEVICES

3D UFET DEVICES AND METHODS FOR MANUFACTURING THE SAME

HIGH PERFORMANCE 3D COMPACT TRANSISTOR ARCHITECTURE

METHODS OF COMPACT CELL DESIGN FOR LOGIC APPLICATIONS

VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS

3D HIGH DENSITY DEVICES INTEGRATED WITH SOURCE AND DRAIN RAILS

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

HIGH DENSITY 3D TRANSPORT DEVICE NANO SHEET

3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTO...

VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME

VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME

THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME

3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC...

TRANSISTOR STACK OF VERTICAL CHANNEL FERROELECTRIC FETS AND METHODS...

THREE-DIMENSIONAL PLURALITY OF N HORIZONTAL MEMORY CELLS WITH ENHAN...

METHOD OF MAKING 3D MEMORY STACKING FORMATION WITH HIGH CIRCUIT DEN...

SILICON NANO SHEET THREE-DIMENSIONAL HORIZONTAL MEMORY WITH ALL-ARO...