Mark R. Gardner

Person

Oxnard, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor stack of vertical channel ferroelectric FETs and methods...
- Patent number 11,978,735
- Issue date May 7, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having channel structure with 2D material
- Patent number 11,942,536
- Issue date Mar 26, 2024
- Tokyo Electron Limited
- Robert D. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for designing three dimensional metal lines for enhanced dev...
- Patent number 11,908,747
- Issue date Feb 20, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple nano layer transistor layers with different transistor arc...
- Patent number 11,894,378
- Issue date Feb 6, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High precision 3D metal stacking for a plurality of 3D devices
- Patent number 11,887,897
- Issue date Jan 30, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a plurality of high density logic elements with ad...
- Patent number 11,876,125
- Issue date Jan 16, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making 3D isolation
- Patent number 11,842,919
- Issue date Dec 12, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional device with self-aligned vertical interconnection
- Patent number 11,830,876
- Issue date Nov 28, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-dimensional vertical switching connections for connecting cir...
- Patent number 11,810,854
- Issue date Nov 7, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple planes of transistors with different transistor architectu...
- Patent number 11,777,015
- Issue date Oct 3, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor apparatus having a silicide between two devices
- Patent number 11,776,954
- Issue date Oct 3, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance floating body VFET with dielectric core
- Patent number 11,769,831
- Issue date Sep 26, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density architecture design for 3D logic and 3D memory circuits
- Patent number 11,764,200
- Issue date Sep 19, 2023
- Tokyo Electron Limited
- Mark Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device layout and method using advanced 3D isolation
- Patent number 11,756,836
- Issue date Sep 12, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized stress regions for three-dimension chiplet formation
- Patent number 11,721,551
- Issue date Aug 8, 2023
- Tokyo Electron Limited
- Anton J. Devilliers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making 3D circuits with integrated stacked 3D metal lines...
- Patent number 11,721,582
- Issue date Aug 8, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making vertical semiconductor nanosheets with diffusion b...
- Patent number 11,721,592
- Issue date Aug 8, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of expanding 3D device architectural designs for enhanced pe...
- Patent number 11,695,058
- Issue date Jul 4, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable connection segment and method of forming the same
- Patent number 11,694,957
- Issue date Jul 4, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized stress regions for three-dimension chiplet formation
- Patent number 11,688,642
- Issue date Jun 27, 2023
- Tokyo Electron Limited
- Anton J. Devilliers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional universal CMOS device
- Patent number 11,652,139
- Issue date May 16, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Horizontal programmable conducting bridges between conductive lines
- Patent number 11,640,937
- Issue date May 2, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D complementary metal oxide semiconductor (CMOS) device and method...
- Patent number 11,631,671
- Issue date Apr 18, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal connections and routing for advanced 3D layout designs
- Patent number 11,626,329
- Issue date Apr 11, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D semiconductor apparatus manufactured with a plurality of substra...
- Patent number 11,610,993
- Issue date Mar 21, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for analysis of DNA fragments
- Patent number 11,597,971
- Issue date Mar 7, 2023
- Life Technologies Corporation
- Barry Merriman
- C12 - BIOCHEMISTRY BEER SPIRITS WINE VINEGAR MICROBIOLOGY ENZYMOLOGY MUTATION...
Information Patent Grant
High performance nanosheet fabrication method with enhanced high mo...
- Patent number 11,594,535
- Issue date Feb 28, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device and method of forming with three-dimensional memory and thre...
- Patent number 11,557,655
- Issue date Jan 17, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optimum high density 3D device layout and method of fabrication
- Patent number 11,557,519
- Issue date Jan 17, 2023
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density 3D layout enhancement of multiple CMOS devices
- Patent number 11,557,657
- Issue date Jan 17, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240145595
- Publication date May 2, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
- Publication number 20240145576
- Publication date May 2, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
- Publication number 20240120407
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D NANOSHEET STACK WITH DUAL SELECTIVE CHANNEL REMOVAL OF HIGH MOBI...
- Publication number 20240120336
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE 3D CHANNELS WITH UPSILON NANOSHEETS
- Publication number 20240120375
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING HIGH PERFORMANCE 3D NANO SHEET DEVICES
- Publication number 20240113114
- Publication date Apr 4, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D UFET DEVICES AND METHODS FOR MANUFACTURING THE SAME
- Publication number 20240105777
- Publication date Mar 28, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE 3D COMPACT TRANSISTOR ARCHITECTURE
- Publication number 20240096708
- Publication date Mar 21, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF COMPACT CELL DESIGN FOR LOGIC APPLICATIONS
- Publication number 20240079475
- Publication date Mar 7, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS
- Publication number 20240079452
- Publication date Mar 7, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D HIGH DENSITY DEVICES INTEGRATED WITH SOURCE AND DRAIN RAILS
- Publication number 20240071871
- Publication date Feb 29, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240063261
- Publication date Feb 22, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240063220
- Publication date Feb 22, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY 3D TRANSPORT DEVICE NANO SHEET
- Publication number 20230402505
- Publication date Dec 14, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTO...
- Publication number 20230378364
- Publication date Nov 23, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
- Publication number 20230378366
- Publication date Nov 23, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
- Publication number 20230369505
- Publication date Nov 16, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME
- Publication number 20230352581
- Publication date Nov 2, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC...
- Publication number 20230337435
- Publication date Oct 19, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR STACK OF VERTICAL CHANNEL FERROELECTRIC FETS AND METHODS...
- Publication number 20230335555
- Publication date Oct 19, 2023
- TOKYO ELECTRON LIMITED
- Mark I. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL PLURALITY OF N HORIZONTAL MEMORY CELLS WITH ENHAN...
- Publication number 20230320069
- Publication date Oct 5, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING 3D MEMORY STACKING FORMATION WITH HIGH CIRCUIT DEN...
- Publication number 20230301061
- Publication date Sep 21, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON NANO SHEET THREE-DIMENSIONAL HORIZONTAL MEMORY WITH ALL-ARO...
- Publication number 20230301059
- Publication date Sep 21, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D MEMORY WITH CELL STACKING USING AN IN-SITU CAPACITOR STACK
- Publication number 20230301058
- Publication date Sep 21, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL SILICON NANOSHEET MEMORY WITH METAL CAPACITOR
- Publication number 20230301060
- Publication date Sep 21, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D HORIZONTAL MEMORY CELL WITH SEQUENTIAL 3D VERTICAL STACKING
- Publication number 20230301062
- Publication date Sep 21, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME
- Publication number 20230282643
- Publication date Sep 7, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
2D GAS CHANNEL FOR VFETS
- Publication number 20230261098
- Publication date Aug 17, 2023
- TOKYO ELECTRON LIMITED
- Robert D. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ADVANCED TRANSISTOR ARCHITECTURE INTEGRATED WITH SOURCE/DRAIN SP...
- Publication number 20230261041
- Publication date Aug 17, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D UFET DEVICE FOR ADVANCED 3D INTEGRATION
- Publication number 20230261113
- Publication date Aug 17, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS

Mark R. Gardner

Person

Patents Grantslast 30 patents

Transistor stack of vertical channel ferroelectric FETs and methods...

Semiconductor device having channel structure with 2D material

Method for designing three dimensional metal lines for enhanced dev...

Multiple nano layer transistor layers with different transistor arc...

High precision 3D metal stacking for a plurality of 3D devices

Method of making a plurality of high density logic elements with ad...

Method of making 3D isolation

Three-dimensional device with self-aligned vertical interconnection

Multi-dimensional vertical switching connections for connecting cir...

Multiple planes of transistors with different transistor architectu...

Semiconductor apparatus having a silicide between two devices

High performance floating body VFET with dielectric core

High density architecture design for 3D logic and 3D memory circuits

3D device layout and method using advanced 3D isolation

Localized stress regions for three-dimension chiplet formation

Method of making 3D circuits with integrated stacked 3D metal lines...

Method of making vertical semiconductor nanosheets with diffusion b...

Method of expanding 3D device architectural designs for enhanced pe...

Programmable connection segment and method of forming the same

Localized stress regions for three-dimension chiplet formation

Three-dimensional universal CMOS device

Horizontal programmable conducting bridges between conductive lines

3D complementary metal oxide semiconductor (CMOS) device and method...

Metal connections and routing for advanced 3D layout designs

3D semiconductor apparatus manufactured with a plurality of substra...

Methods for analysis of DNA fragments

High performance nanosheet fabrication method with enhanced high mo...

Device and method of forming with three-dimensional memory and thre...

Optimum high density 3D device layout and method of fabrication

High density 3D layout enhancement of multiple CMOS devices

Patents Applicationslast 30 patents

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

3D NANOSHEET STACK WITH DUAL SELECTIVE CHANNEL REMOVAL OF HIGH MOBI...

HIGH PERFORMANCE 3D CHANNELS WITH UPSILON NANOSHEETS

METHODS FOR FORMING HIGH PERFORMANCE 3D NANO SHEET DEVICES

3D UFET DEVICES AND METHODS FOR MANUFACTURING THE SAME

HIGH PERFORMANCE 3D COMPACT TRANSISTOR ARCHITECTURE

METHODS OF COMPACT CELL DESIGN FOR LOGIC APPLICATIONS

VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS

3D HIGH DENSITY DEVICES INTEGRATED WITH SOURCE AND DRAIN RAILS

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

HIGH DENSITY 3D TRANSPORT DEVICE NANO SHEET

3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTO...

VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME

VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME

THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME

3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC...

TRANSISTOR STACK OF VERTICAL CHANNEL FERROELECTRIC FETS AND METHODS...

THREE-DIMENSIONAL PLURALITY OF N HORIZONTAL MEMORY CELLS WITH ENHAN...

METHOD OF MAKING 3D MEMORY STACKING FORMATION WITH HIGH CIRCUIT DEN...

SILICON NANO SHEET THREE-DIMENSIONAL HORIZONTAL MEMORY WITH ALL-ARO...

3D MEMORY WITH CELL STACKING USING AN IN-SITU CAPACITOR STACK

THREE-DIMENSIONAL SILICON NANOSHEET MEMORY WITH METAL CAPACITOR

3D HORIZONTAL MEMORY CELL WITH SEQUENTIAL 3D VERTICAL STACKING

THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME

2D GAS CHANNEL FOR VFETS

3D ADVANCED TRANSISTOR ARCHITECTURE INTEGRATED WITH SOURCE/DRAIN SP...

3D UFET DEVICE FOR ADVANCED 3D INTEGRATION