MARK S. BIRRITTELLA

Person

Chippewa Falls, WI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Coordinating width changes for an active network link
- Patent number 10,491,472
- Issue date Nov 26, 2019
- Intel Corporation
- Brent R. Rothermel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Exascale fabric time synchronization
- Patent number 10,372,647
- Issue date Aug 6, 2019
- Intel Corporation
- Thomas D. Lovett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliable transport of ethernet packet data with wire-speed and pack...
- Patent number 10,305,802
- Issue date May 28, 2019
- Intel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hierarchical/lossless packet preemption to reduce latency jitter in...
- Patent number 10,230,665
- Issue date Mar 12, 2019
- Intel Corporation
- Thomas D. Lovett
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multichip package link
- Patent number 9,946,676
- Issue date Apr 17, 2018
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lane error detection and lane removal mechanism to reduce the proba...
- Patent number 9,887,804
- Issue date Feb 6, 2018
- Intel Corporation
- Mark S. Birrittella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient link layer retry protocol utilizing implicit acknowledgem...
- Patent number 9,819,452
- Issue date Nov 14, 2017
- Intel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reliable transport of ethernet packet data with wire-speed and pack...
- Patent number 9,628,382
- Issue date Apr 18, 2017
- Intel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient link layer retry protocol utilizing implicit acknowledgem...
- Patent number 9,397,792
- Issue date Jul 19, 2016
- Intel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Lane error detection and lane removal mechanism to reduce the proba...
- Patent number 9,325,449
- Issue date Apr 26, 2016
- Intel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link transfer, bit error detection and link retry using flit bundle...
- Patent number 9,306,863
- Issue date Apr 5, 2016
- Intel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transistor level verilog
- Patent number 7,587,305
- Issue date Sep 8, 2009
- Cray Inc.
- Robert J. Lutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock signal duty cycle adjust circuit
- Patent number 6,992,515
- Issue date Jan 31, 2006
- Cray, Inc.
- Mark S. Birrittella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for phase detector circuit with reduced offset
- Patent number 6,836,153
- Issue date Dec 28, 2004
- Cray, Inc.
- Mark S. Birrittella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit design for high-speed digital communication
- Patent number 6,775,339
- Issue date Aug 10, 2004
- Silicon Graphics, Inc.
- Paul T. Wildes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register scoreboarding to support overlapped execution of vector me...
- Patent number 6,266,759
- Issue date Jul 24, 2001
- Cray, Inc.
- Mark S. Birrittella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Networked multiprocessor system with global distributed memory and...
- Patent number 5,797,035
- Issue date Aug 18, 1998
- Cray Research, Inc.
- Mark S. Birrittella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor computer system with interleaved processing element...
- Patent number 5,737,628
- Issue date Apr 7, 1998
- Cray Research, Inc.
- Mark S. Birrittella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for allocating messages between virtual channels to avoid de...
- Patent number 5,583,990
- Issue date Dec 10, 1996
- Cray Research, Inc.
- Mark S. Birrittella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emitter emitter logic (EEL) and emitter collector dotted logic (ECD...
- Patent number 5,182,473
- Issue date Jan 26, 1993
- Cray Research, Inc.
- Jan A. Wikstrom
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
ECL latch with single-ended and differential inputs
- Patent number 5,177,380
- Issue date Jan 5, 1993
- Cray Research, Inc.
- Mark S. Birrittella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
READ-WHILE-WRITE RAM CELL
- Patent number 4,964,081
- Issue date Oct 16, 1990
- Cray Research, Inc.
- Mark S. Birrittella
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
COORDINATING WIDTH CHANGES FOR AN ACTIVE NETWORK LINK
- Publication number 20180191570
- Publication date Jul 5, 2018
- Intel Corporation
- Brent R. ROTHERMEL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RELIABLE TRANSPORT OF ETHERNET PACKET DATA WITH WIRE-SPEED AND PACK...
- Publication number 20170237659
- Publication date Aug 17, 2017
- Intel Corporation
- Mark S Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EXASCALE FABRIC TIME SYNCHRONIZATION
- Publication number 20170177527
- Publication date Jun 22, 2017
- THOMAS D. LOVETT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LANE ERROR DETECTION AND LANE REMOVAL MECHANISM TO REDUCE THE PROBA...
- Publication number 20170026149
- Publication date Jan 26, 2017
- lntel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENT LINK LAYER RETRY PROTOCOL UTILIZING IMPLICIT ACKNOWLEDGEM...
- Publication number 20170026150
- Publication date Jan 26, 2017
- lntel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTICHIP PACKAGE LINK
- Publication number 20160283429
- Publication date Sep 29, 2016
- Intel Corporation
- Mahesh Wagh
- G01 - MEASURING TESTING
Information Patent Application
LINK LAYER SIGNAL SYNCHRONIZATION
- Publication number 20160132072
- Publication date May 12, 2016
- Intel Corporation
- Mark S. Birrittella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSPORT OF ETHERNET PACKET DATA WITH WIRE-SPEED AND PACKET DATA R...
- Publication number 20150222533
- Publication date Aug 6, 2015
- Intel Corporation
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIERARCHICAL/LOSSLESS PACKET PREEMPTION TO REDUCE LATENCY JITTER IN...
- Publication number 20150180799
- Publication date Jun 25, 2015
- Thomas D. Lovett
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LINK TRANSFER, BIT ERROR DETECTION AND LINK RETRY USING FLIT BUNDLE...
- Publication number 20150163170
- Publication date Jun 11, 2015
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENT LINK LAYER RETRY PROTOCOL UTILIZING IMPLICIT ACKNOWLEDGEM...
- Publication number 20150163019
- Publication date Jun 11, 2015
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LANE ERROR DETECTION AND LANE REMOVAL MECHANISM TO REDUCE THE PROBA...
- Publication number 20150163014
- Publication date Jun 11, 2015
- Mark S. Birrittella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Systems and methods for phase detector circuit with reduced offset
- Publication number 20040150446
- Publication date Aug 5, 2004
- Cray Inc.
- Mark S. Birrittella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Transistor level verilog
- Publication number 20040002846
- Publication date Jan 1, 2004
- Cray Inc.
- Robert J. Lutz
- G06 - COMPUTING CALCULATING COUNTING

MARK S. BIRRITTELLA

Person

Patents Grantslast 30 patents

Coordinating width changes for an active network link

Exascale fabric time synchronization

Reliable transport of ethernet packet data with wire-speed and pack...

Hierarchical/lossless packet preemption to reduce latency jitter in...

Multichip package link

Lane error detection and lane removal mechanism to reduce the proba...

Efficient link layer retry protocol utilizing implicit acknowledgem...

Reliable transport of ethernet packet data with wire-speed and pack...

Efficient link layer retry protocol utilizing implicit acknowledgem...

Lane error detection and lane removal mechanism to reduce the proba...

Link transfer, bit error detection and link retry using flit bundle...

Transistor level verilog

Clock signal duty cycle adjust circuit

Systems and methods for phase detector circuit with reduced offset

Circuit design for high-speed digital communication

Register scoreboarding to support overlapped execution of vector me...

Networked multiprocessor system with global distributed memory and...

Multiprocessor computer system with interleaved processing element...

System for allocating messages between virtual channels to avoid de...

Emitter emitter logic (EEL) and emitter collector dotted logic (ECD...

ECL latch with single-ended and differential inputs

READ-WHILE-WRITE RAM CELL

Patents Applicationslast 30 patents

COORDINATING WIDTH CHANGES FOR AN ACTIVE NETWORK LINK

RELIABLE TRANSPORT OF ETHERNET PACKET DATA WITH WIRE-SPEED AND PACK...

EXASCALE FABRIC TIME SYNCHRONIZATION

LANE ERROR DETECTION AND LANE REMOVAL MECHANISM TO REDUCE THE PROBA...

EFFICIENT LINK LAYER RETRY PROTOCOL UTILIZING IMPLICIT ACKNOWLEDGEM...

MULTICHIP PACKAGE LINK

LINK LAYER SIGNAL SYNCHRONIZATION

TRANSPORT OF ETHERNET PACKET DATA WITH WIRE-SPEED AND PACKET DATA R...

HIERARCHICAL/LOSSLESS PACKET PREEMPTION TO REDUCE LATENCY JITTER IN...

LINK TRANSFER, BIT ERROR DETECTION AND LINK RETRY USING FLIT BUNDLE...

EFFICIENT LINK LAYER RETRY PROTOCOL UTILIZING IMPLICIT ACKNOWLEDGEM...

LANE ERROR DETECTION AND LANE REMOVAL MECHANISM TO REDUCE THE PROBA...

Systems and methods for phase detector circuit with reduced offset

Transistor level verilog