Mark S. Hlad

Person

Gainsville, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Substrate conductor structure and method
- Patent number 10,734,282
- Issue date Aug 4, 2020
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate conductor structure and method
- Patent number 10,121,701
- Issue date Nov 6, 2018
- Intel Corporation
- Harold Ryan Chase
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Organic thin film passivation of metal interconnections
- Patent number 9,824,991
- Issue date Nov 21, 2017
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Organic thin film passivation of metal interconnections
- Patent number 9,583,390
- Issue date Feb 28, 2017
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate conductor structure and method
- Patent number 9,406,587
- Issue date Aug 2, 2016
- Intel Corporation
- Harold Ryan Chase
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Device packaging with substrates having embedded lines and metal de...
- Patent number 9,355,952
- Issue date May 31, 2016
- Intel Corporation
- Mark S Hlad
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Enabling package-on-package (PoP) pad surface finishes on bumpless...
- Patent number 9,299,602
- Issue date Mar 29, 2016
- Intel Corporation
- Qinglei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Organic thin film passivation of metal interconnections
- Patent number 9,257,276
- Issue date Feb 9, 2016
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-cylindrical conducting shapes in multilayer laminated substrate...
- Patent number 9,198,293
- Issue date Nov 24, 2015
- Intel Corporation
- Harold R. Chase
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Enabling package-on-package (PoP) pad surface finishes on bumpless...
- Patent number 9,190,315
- Issue date Nov 17, 2015
- Intel Corporation
- Qinglei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Device packaging with substrates having embedded lines and metal de...
- Patent number 9,093,313
- Issue date Jul 28, 2015
- Intel Corporation
- Mark S Hlad
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Providing a void-free filled interconnect structure in a layer of p...
- Patent number 8,877,632
- Issue date Nov 4, 2014
- Intel Corporation
- Amanda E. Schuckman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device packaging with substrates having embedded lines and metal de...
- Patent number 8,835,217
- Issue date Sep 16, 2014
- Intel Corporation
- Mark S Hlad
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bumpless build-up layer and laminated core hybrid structures and me...
- Patent number 8,809,124
- Issue date Aug 19, 2014
- Intel Corporation
- Mathew J. Manusharow
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bumpless build-up layer and laminated core hybrid structures and me...
- Patent number 8,508,037
- Issue date Aug 13, 2013
- Intel Corporation
- Mathew J. Manusharow
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of making substrate package with through holes for high spee...
- Patent number 8,353,101
- Issue date Jan 15, 2013
- Intel Corporation
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Barrier layer for fine-pitch mask-based substrate bumping
- Patent number 8,183,692
- Issue date May 22, 2012
- Intel Corporation
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods for fabricating fine line/space (FLS) routing in high densi...
- Patent number 7,919,408
- Issue date Apr 5, 2011
- Intel Corporation
- Mark S. Hlad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate package with through holes for high speed I/O flex cable
- Patent number 7,888,784
- Issue date Feb 15, 2011
- Intel Corporation
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Barrier layer for fine-pitch mask-based substrate bumping
- Patent number 7,776,734
- Issue date Aug 17, 2010
- Intel Corporation
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
SUBSTRATE CONDUCTOR STRUCTURE AND METHOD
- Publication number 20190027405
- Publication date Jan 24, 2019
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC ASSEMBLY THAT INCLUDES VOID FREE HOLES
- Publication number 20180288885
- Publication date Oct 4, 2018
- Sri Ranga Sai Boyapati
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS
- Publication number 20170141061
- Publication date May 18, 2017
- Intel Corporation
- Aleksandar ALEKSOV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE CONDUCTOR STRUCTURE AND METHOD
- Publication number 20160336223
- Publication date Nov 17, 2016
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS
- Publication number 20160155667
- Publication date Jun 2, 2016
- Intel Corporation
- Aleksandar ALEKSOV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DE...
- Publication number 20150318238
- Publication date Nov 5, 2015
- Intel Corporation
- Mark S. Hlad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DE...
- Publication number 20150008578
- Publication date Jan 8, 2015
- Intel Corporation
- Mark S. Hlad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROVIDING A VOID-FREE FILLED INTERCONNECT STRUCTURE IN A LAYER OF A...
- Publication number 20140332974
- Publication date Nov 13, 2014
- Amanda E. Schuckman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-CYLINDRICAL CONDUCTING SHAPES IN MULTILAYER LAMINATED SUBSTRATE...
- Publication number 20140197545
- Publication date Jul 17, 2014
- Harold R. Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS
- Publication number 20140138818
- Publication date May 22, 2014
- Alexsandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE CONDUCTOR STRUCTURE AND METHOD
- Publication number 20130341772
- Publication date Dec 26, 2013
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND ME...
- Publication number 20130344662
- Publication date Dec 26, 2013
- Mathew J. Manusharow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS...
- Publication number 20130320547
- Publication date Dec 5, 2013
- Qinglei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DE...
- Publication number 20120161330
- Publication date Jun 28, 2012
- Intel Corporation
- Mark S. Hlad
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND ME...
- Publication number 20120139116
- Publication date Jun 7, 2012
- Mathew J. Manusharow
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE
- Publication number 20110108427
- Publication date May 12, 2011
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
BARRIER LAYER FOR FINE-PITCH MASK-BASED SUBSTRATE BUMPING
- Publication number 20100276185
- Publication date Nov 4, 2010
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE
- Publication number 20100078826
- Publication date Apr 1, 2010
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHODS FOR FABRICATING FINE LINE/SPACE (FLS) ROUTING IN HIGH DENSI...
- Publication number 20090325379
- Publication date Dec 31, 2009
- Mark S. Hlad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barrier layer for fine-pitch mask-based substrate bumping
- Publication number 20070275550
- Publication date Nov 29, 2007
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Mark S. Hlad

Person

Patents Grantslast 30 patents

Substrate conductor structure and method

Substrate conductor structure and method

Organic thin film passivation of metal interconnections

Organic thin film passivation of metal interconnections

Substrate conductor structure and method

Device packaging with substrates having embedded lines and metal de...

Enabling package-on-package (PoP) pad surface finishes on bumpless...

Organic thin film passivation of metal interconnections

Non-cylindrical conducting shapes in multilayer laminated substrate...

Enabling package-on-package (PoP) pad surface finishes on bumpless...

Device packaging with substrates having embedded lines and metal de...

Providing a void-free filled interconnect structure in a layer of p...

Device packaging with substrates having embedded lines and metal de...

Bumpless build-up layer and laminated core hybrid structures and me...

Bumpless build-up layer and laminated core hybrid structures and me...

Method of making substrate package with through holes for high spee...

Barrier layer for fine-pitch mask-based substrate bumping

Methods for fabricating fine line/space (FLS) routing in high densi...

Substrate package with through holes for high speed I/O flex cable

Barrier layer for fine-pitch mask-based substrate bumping

Patents Applicationslast 30 patents

SUBSTRATE CONDUCTOR STRUCTURE AND METHOD

ELECTRONIC ASSEMBLY THAT INCLUDES VOID FREE HOLES

ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS

SUBSTRATE CONDUCTOR STRUCTURE AND METHOD

ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DE...

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DE...

PROVIDING A VOID-FREE FILLED INTERCONNECT STRUCTURE IN A LAYER OF A...

NON-CYLINDRICAL CONDUCTING SHAPES IN MULTILAYER LAMINATED SUBSTRATE...

ORGANIC THIN FILM PASSIVATION OF METAL INTERCONNECTIONS

SUBSTRATE CONDUCTOR STRUCTURE AND METHOD

BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND ME...

ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS...

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DE...

BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND ME...

SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE

BARRIER LAYER FOR FINE-PITCH MASK-BASED SUBSTRATE BUMPING

SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE

METHODS FOR FABRICATING FINE LINE/SPACE (FLS) ROUTING IN HIGH DENSI...

Barrier layer for fine-pitch mask-based substrate bumping