Mark Sean Hefty

Person

Aloha, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Writes to multiple memory destinations
- Patent number 12,117,956
- Issue date Oct 15, 2024
- Intel Corporation
- Mark Sean Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
At least one mechanism to permit, at least in part, allocation and/...
- Patent number 11,246,027
- Issue date Feb 8, 2022
- Intel Corporation
- William R. Magro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Remote direct memory access with reduced latency
- Patent number 10,334,047
- Issue date Jun 25, 2019
- Intel Corporation
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for RDMA with commit ACKs
- Patent number 10,055,371
- Issue date Aug 21, 2018
- Intel Corporation
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Remote direct memory access with reduced latency
- Patent number 9,774,677
- Issue date Sep 26, 2017
- Intel Corporation
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Peer-to-peer interrupt signaling between devices coupled via interc...
- Patent number 9,749,413
- Issue date Aug 29, 2017
- Intel Corporation
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low latency cluster computing
- Patent number 9,560,117
- Issue date Jan 31, 2017
- Intel Corporation
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient distribution of subnet administration data over an RDMA n...
- Patent number 9,495,324
- Issue date Nov 15, 2016
- Intel Corporation
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Continuous information transfer with reduced latency
- Patent number 9,490,988
- Issue date Nov 8, 2016
- Intel Corporation
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
At least one mechanism to permit, at least in part, allocation and/...
- Patent number 9,479,506
- Issue date Oct 25, 2016
- Intel Corporation
- William R. Magro
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
GID capable switching in an infiniband fabric
- Patent number 9,288,160
- Issue date Mar 15, 2016
- Intel Corporation
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Direct I/O access for system co-processors
- Patent number 8,914,556
- Issue date Dec 16, 2014
- Intel Corporation
- William R. Magro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for communicating between memory regions
- Patent number 8,583,755
- Issue date Nov 12, 2013
- Intel Corporation
- Mark Sean Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for communicating between memory regions
- Patent number 8,250,165
- Issue date Aug 21, 2012
- Intel Corporation
- Mark Sean Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for communicating between memory regions
- Patent number 8,099,471
- Issue date Jan 17, 2012
- Intel Corporation
- Mark Sean Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable network interface card
- Patent number 7,948,979
- Issue date May 24, 2011
- Intel Corporation
- Mark Sean Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for communication between memory regions
- Patent number 7,624,156
- Issue date Nov 24, 2009
- Intel Corporation
- Mark Sean Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronization mechanism and method for synchronizing multiple thr...
- Patent number 7,143,410
- Issue date Nov 28, 2006
- Intel Corporation
- Jerrie L. Coffman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and systems for flow control of transmissions over channel-b...
- Patent number 6,735,174
- Issue date May 11, 2004
- Intel Corporation
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Completion queue management mechanism and method for checking on mu...
- Patent number 6,718,370
- Issue date Apr 6, 2004
- Intel Corporation
- Jerrie L. Coffman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and system for message resource pool with asynchronous and...
- Patent number 6,553,438
- Issue date Apr 22, 2003
- Intel Corporation
- Jerrie L. Coffman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AT LEAST ONE MECHANISM TO PERMIT, AT LEAST IN PART, ALLOCATION AND/...
- Publication number 20220210639
- Publication date Jun 30, 2022
- Intel Corporation
- WILLIAM R. MAGRO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITES TO MULTIPLE MEMORY DESTINATIONS
- Publication number 20200133909
- Publication date Apr 30, 2020
- Intel Corporation
- Mark Sean HEFTY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOTE DIRECT MEMORY ACCESS WITH REDUCED LATENCY
- Publication number 20180146038
- Publication date May 24, 2018
- Intel Corporation
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT LEAST ONE MECHANISM TO PERMIT, AT LEAST IN PART, ALLOCATION AND/...
- Publication number 20170104692
- Publication date Apr 13, 2017
- Intel Corporation
- WILLIAM R. MAGRO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for RDMA with Commit ACKs
- Publication number 20160124877
- Publication date May 5, 2016
- Intel Corporation
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT LEAST ONE MECHANISM TO PERMIT, AT LEAST IN PART, ALLOCATION AND/...
- Publication number 20150305006
- Publication date Oct 22, 2015
- WILLIAM R. MAGRO
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Scalable Address Resolution
- Publication number 20150264116
- Publication date Sep 17, 2015
- Ira Weiny
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PEER-TO-PEER INTERRUPT SIGNALING BETWEEN DEVICES COUPLED VIA INTERC...
- Publication number 20140250202
- Publication date Sep 4, 2014
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTINUOUS INFORMATION TRANSFER WITH REDUCED LATENCY
- Publication number 20140207896
- Publication date Jul 24, 2014
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOTE DIRECT MEMORY ACCESS WITH REDUCED LATENCY
- Publication number 20140201306
- Publication date Jul 17, 2014
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY CLUSTER COMPUTING
- Publication number 20140129635
- Publication date May 8, 2014
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT I/O ACCESS FOR SYSTEM CO-PROCESSORS
- Publication number 20130275631
- Publication date Oct 17, 2013
- William R. Magro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DISTRIBUTION OF SUBNET ADMINISTRATION DATA OVER AN RDMA N...
- Publication number 20130262613
- Publication date Oct 3, 2013
- Mark S. Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GID CAPABLE SWITCHING IN AN INFINIBAND FABRIC
- Publication number 20130259033
- Publication date Oct 3, 2013
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR COMMUNICATING BETWEEN MEMORY REGIONS
- Publication number 20120284355
- Publication date Nov 8, 2012
- Mark Sean Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR COMMUNICATING BETWEEN MEMORY REGIONS
- Publication number 20120084380
- Publication date Apr 5, 2012
- Mark Sean Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR COMMUNICATING BETWEEN MEMORY REGIONS
- Publication number 20100146069
- Publication date Jun 10, 2010
- Mark Sean Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE NETWORK INTERFACE CARD
- Publication number 20090296699
- Publication date Dec 3, 2009
- Mark Sean Hefty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and systems for flow control of transmissions over channel-...
- Publication number 20040076116
- Publication date Apr 22, 2004
- Mark S. Hefty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for communications management and control over an...
- Publication number 20020087720
- Publication date Jul 4, 2002
- Arlin R. Davis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Mark Sean Hefty

Person

Patents Grantslast 30 patents

Writes to multiple memory destinations

At least one mechanism to permit, at least in part, allocation and/...

Remote direct memory access with reduced latency

Apparatus and method for RDMA with commit ACKs

Remote direct memory access with reduced latency

Peer-to-peer interrupt signaling between devices coupled via interc...

Low latency cluster computing

Efficient distribution of subnet administration data over an RDMA n...

Continuous information transfer with reduced latency

At least one mechanism to permit, at least in part, allocation and/...

GID capable switching in an infiniband fabric

Direct I/O access for system co-processors

Method and system for communicating between memory regions

Method and system for communicating between memory regions

Method and system for communicating between memory regions

Programmable network interface card

Method and system for communication between memory regions

Synchronization mechanism and method for synchronizing multiple thr...

Method and systems for flow control of transmissions over channel-b...

Completion queue management mechanism and method for checking on mu...

Methods and system for message resource pool with asynchronous and...

Patents Applicationslast 30 patents

AT LEAST ONE MECHANISM TO PERMIT, AT LEAST IN PART, ALLOCATION AND/...

WRITES TO MULTIPLE MEMORY DESTINATIONS

REMOTE DIRECT MEMORY ACCESS WITH REDUCED LATENCY

AT LEAST ONE MECHANISM TO PERMIT, AT LEAST IN PART, ALLOCATION AND/...

Apparatus and Method for RDMA with Commit ACKs

AT LEAST ONE MECHANISM TO PERMIT, AT LEAST IN PART, ALLOCATION AND/...

Scalable Address Resolution

PEER-TO-PEER INTERRUPT SIGNALING BETWEEN DEVICES COUPLED VIA INTERC...

CONTINUOUS INFORMATION TRANSFER WITH REDUCED LATENCY

REMOTE DIRECT MEMORY ACCESS WITH REDUCED LATENCY

LOW LATENCY CLUSTER COMPUTING

DIRECT I/O ACCESS FOR SYSTEM CO-PROCESSORS

EFFICIENT DISTRIBUTION OF SUBNET ADMINISTRATION DATA OVER AN RDMA N...

GID CAPABLE SWITCHING IN AN INFINIBAND FABRIC

METHOD AND SYSTEM FOR COMMUNICATING BETWEEN MEMORY REGIONS

METHOD AND SYSTEM FOR COMMUNICATING BETWEEN MEMORY REGIONS

METHOD AND SYSTEM FOR COMMUNICATING BETWEEN MEMORY REGIONS

PROGRAMMABLE NETWORK INTERFACE CARD

Methods and systems for flow control of transmissions over channel-...

System and method for communications management and control over an...