Mark Thomann

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Testing fuse configurations in semiconductor devices
- Patent number 10,302,696
- Issue date May 28, 2019
- Rambus Inc.
- Adrian E. Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing fuse configurations in semiconductor devices
- Patent number 9,568,544
- Issue date Feb 14, 2017
- Rambus Inc.
- Adrian E. Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing fuse configurations in semiconductor devices
- Patent number 8,717,052
- Issue date May 6, 2014
- Rambus Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Testing fuse configurations in semiconductor devices
- Patent number 8,063,650
- Issue date Nov 22, 2011
- Rambus Inc.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing a memory device with compressed da...
- Patent number 7,562,268
- Issue date Jul 14, 2009
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Double data rate scheme for data output
- Patent number 7,251,715
- Issue date Jul 31, 2007
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Double data rate scheme for data output
- Patent number 7,093,095
- Issue date Aug 15, 2006
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing a memory device with compressed da...
- Patent number 6,976,195
- Issue date Dec 13, 2005
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop control circuit
- Patent number 6,954,388
- Issue date Oct 11, 2005
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller for delay locked loop circuits
- Patent number 6,901,013
- Issue date May 31, 2005
- Micron Technology, Inc.
- William Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reducing standby current during power down mode
- Patent number 6,836,437
- Issue date Dec 28, 2004
- Micron Technology, Inc.
- Wen Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller for delay locked loop circuits
- Patent number 6,809,974
- Issue date Oct 26, 2004
- Micron Technology, Inc.
- William Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop control circuit
- Patent number 6,809,990
- Issue date Oct 26, 2004
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Read/write timing calibration of a memory array using a row or a re...
- Patent number 6,763,444
- Issue date Jul 13, 2004
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Double data rate scheme for data output
- Patent number 6,694,416
- Issue date Feb 17, 2004
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reducing standby current during power down mode
- Patent number 6,665,219
- Issue date Dec 16, 2003
- Micron Technology, Inc.
- Wen Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared buffer memory architecture for asynchronous transfer mode sw...
- Patent number 6,487,207
- Issue date Nov 26, 2002
- Micron Technology, Inc.
- Mark R. Thomann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of reducing standby current during power down mode
- Patent number 6,438,060
- Issue date Aug 20, 2002
- Micron Technology, Inc.
- Wen Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential input buffer bias circuit
- Patent number 6,392,453
- Issue date May 21, 2002
- Micron Technology, Inc.
- Christopher K. Morzano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed I/O calibration using an input path and simplified logic
- Patent number 6,330,194
- Issue date Dec 11, 2001
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit power-up controllers, integrated circuit power-u...
- Patent number 6,201,751
- Issue date Mar 13, 2001
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared buffer memory architecture for asynchronous transfer mode sw...
- Patent number 6,081,528
- Issue date Jun 27, 2000
- Micron Technology, Inc.
- Mark R. Thomann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for a high speed cyclical redundancy check system
- Patent number 5,964,896
- Issue date Oct 12, 1999
- Micron Technology, Inc.
- Mark Thomann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transfer in a memory device having complete row redundancy
- Patent number 5,953,258
- Issue date Sep 14, 1999
- Micron Technology, Inc.
- Mark R. Thomann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhanced booting and DC conditions
- Patent number 5,945,845
- Issue date Aug 31, 1999
- Micron Technology, Inc.
- Mark R. Thomann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for a high speed cyclical redundancy check system
- Patent number 5,854,800
- Issue date Dec 29, 1998
- Micron Technlogy, Inc.
- Mark Thomann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable data port clocking system with automatic disable and n...
- Patent number 5,838,959
- Issue date Nov 17, 1998
- Micron Technology, Inc.
- Mark Thomann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having complete row redundancy
- Patent number 5,815,447
- Issue date Sep 29, 1998
- Micron Technology, Inc.
- Mark R. Thomann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhanced booting and DC conditions
- Patent number 5,783,948
- Issue date Jul 21, 1998
- Micron Technology, Inc.
- Mark R. Thomann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit for transferring data with dynamic parity genera...
- Patent number 5,778,007
- Issue date Jul 7, 1998
- Micron Technology, Inc.
- Mark Thomann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES
- Publication number 20170176533
- Publication date Jun 22, 2017
- RAMBUS INC.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES
- Publication number 20140333341
- Publication date Nov 13, 2014
- RAMBUS INC.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES
- Publication number 20110291693
- Publication date Dec 1, 2011
- RAMBUS INC.
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
Testing fuse configurations in semiconductor devices
- Publication number 20080278190
- Publication date Nov 13, 2008
- Adrian E. Ong
- G01 - MEASURING TESTING
Information Patent Application
DOUBLE DATA RATE SCHEME FOR DATA OUTPUT
- Publication number 20060198234
- Publication date Sep 7, 2006
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for testing a memory device with compressed da...
- Publication number 20060090108
- Publication date Apr 27, 2006
- Micron Technology, Inc.
- Mirmajid Seyyedy
- G11 - INFORMATION STORAGE
Information Patent Application
Delay locked loop control circuit
- Publication number 20050024985
- Publication date Feb 3, 2005
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Application
Double data rate scheme for data output
- Publication number 20040117543
- Publication date Jun 17, 2004
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Application
Method of reducing standby current during power down mode
- Publication number 20040042282
- Publication date Mar 4, 2004
- Wen Li
- G11 - INFORMATION STORAGE
Information Patent Application
Delay locked loop control circuit
- Publication number 20030235106
- Publication date Dec 25, 2003
- Micron Technology, Inc.
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Application
Controller for delay locked loop circuits
- Publication number 20020191462
- Publication date Dec 19, 2002
- Micron Technology, Inc.
- William Jones
- G11 - INFORMATION STORAGE
Information Patent Application
Method of characterizing a delay locked loop
- Publication number 20020181296
- Publication date Dec 5, 2002
- William Jones
- G11 - INFORMATION STORAGE
Information Patent Application
Method of reducing standby current during power down mode
- Publication number 20020181299
- Publication date Dec 5, 2002
- Wen Li
- G11 - INFORMATION STORAGE
Information Patent Application
Read/write timing calibration of a memory array using a row or a re...
- Publication number 20020169922
- Publication date Nov 14, 2002
- Mark R. Thomann
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF REDUCING STANDBY CURRENT DURING POWER DOWN MODE
- Publication number 20020110035
- Publication date Aug 15, 2002
- Wen Li
- G11 - INFORMATION STORAGE

Mark Thomann

Person

Patents Grantslast 30 patents

Testing fuse configurations in semiconductor devices

Testing fuse configurations in semiconductor devices

Testing fuse configurations in semiconductor devices

Testing fuse configurations in semiconductor devices

Method and apparatus for testing a memory device with compressed da...

Double data rate scheme for data output

Double data rate scheme for data output

Method and apparatus for testing a memory device with compressed da...

Delay locked loop control circuit

Controller for delay locked loop circuits

Method of reducing standby current during power down mode

Controller for delay locked loop circuits

Delay locked loop control circuit

Read/write timing calibration of a memory array using a row or a re...

Double data rate scheme for data output

Method of reducing standby current during power down mode

Shared buffer memory architecture for asynchronous transfer mode sw...

Method of reducing standby current during power down mode

Differential input buffer bias circuit

High speed I/O calibration using an input path and simplified logic

Integrated circuit power-up controllers, integrated circuit power-u...

Shared buffer memory architecture for asynchronous transfer mode sw...

Method and apparatus for a high speed cyclical redundancy check system

Data transfer in a memory device having complete row redundancy

Method and apparatus for enhanced booting and DC conditions

Method and apparatus for a high speed cyclical redundancy check system

Programmable data port clocking system with automatic disable and n...

Memory device having complete row redundancy

Method and apparatus for enhanced booting and DC conditions

Method and circuit for transferring data with dynamic parity genera...

Patents Applicationslast 30 patents

TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES

TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES

TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES

Testing fuse configurations in semiconductor devices

DOUBLE DATA RATE SCHEME FOR DATA OUTPUT

Method and apparatus for testing a memory device with compressed da...

Delay locked loop control circuit

Double data rate scheme for data output

Method of reducing standby current during power down mode

Delay locked loop control circuit

Controller for delay locked loop circuits

Method of characterizing a delay locked loop

Method of reducing standby current during power down mode

Read/write timing calibration of a memory array using a row or a re...

METHOD OF REDUCING STANDBY CURRENT DURING POWER DOWN MODE