Mark Thomas McCormack

Person

Livermore, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit metallic ion diffusion defect validation
- Patent number 10,910,281
- Issue date Feb 2, 2021
- Microsoft Technology Licensing, LLC
- Mark Thomas McCormack
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Graphic formation via material ablation
- Patent number 9,661,770
- Issue date May 23, 2017
- Microsoft Technology Licensing, LLC
- Mark Thomas McCormack
- B44 - DECORATIVE ARTS
Information Patent Grant
Electronic device with plated electrical contact
- Patent number 9,563,233
- Issue date Feb 7, 2017
- Microsoft Technology Licensing, LLC
- Mark Thomas McCormack
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Method of embedding components in multi-layer circuit boards
- Patent number 7,513,037
- Issue date Apr 7, 2009
- Fujitsu Limited
- Mark Thomas McCormack
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for wafer level testing of integrated optical...
- Patent number 7,386,197
- Issue date Jun 10, 2008
- Intel Corporation
- Dmitri E. Nikonov
- G01 - MEASURING TESTING
Information Patent Grant
Structure and method for embedding capacitors in z-connected multi-...
- Patent number 7,199,307
- Issue date Apr 3, 2007
- Fujitsu Limited
- Mark Thomas McCormack
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-chip module and method for forming and method for deplating d...
- Patent number 6,882,045
- Issue date Apr 19, 2005
- Thomas J. Massingill
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for joining large substrates
- Patent number 6,866,741
- Issue date Mar 15, 2005
- Fujitsu Limited
- Albert W. Chan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for wafer level testing of integrated optical...
- Patent number 6,859,587
- Issue date Feb 22, 2005
- Intel Corporation
- Dmitri E. Nikonov
- G01 - MEASURING TESTING
Information Patent Grant
Structure and method for embedding capacitors in z-connected multi-...
- Patent number 6,759,257
- Issue date Jul 6, 2004
- Fujitsu Limited
- Mark Thomas McCormack
- G11 - INFORMATION STORAGE
Information Patent Grant
Optical coupling structures and the fabrication processes
- Patent number 6,684,007
- Issue date Jan 27, 2004
- Fujitsu Limited
- Tetsuzo Yoshimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Device transfer method
- Patent number 6,669,801
- Issue date Dec 30, 2003
- Fujitsu Limited
- Tetsuzo Yoshimura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer and method for producing a light-guiding structure
- Patent number 6,603,915
- Issue date Aug 5, 2003
- Fujitsu Limited
- Alexei Glebov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive composition
- Patent number 6,579,474
- Issue date Jun 17, 2003
- Fujitsu Limited
- Mark Thomas McCormack
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods for fabricating flexible circuit structures
- Patent number 6,572,780
- Issue date Jun 3, 2003
- Fujitsu Limited
- Mark Thomas McCormack
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods for detaching a layer from a substrate
- Patent number 6,544,430
- Issue date Apr 8, 2003
- Fujitsu Limited
- Mark Thomas McCormack
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Composite interposer and method for producing a composite interposer
- Patent number 6,521,530
- Issue date Feb 18, 2003
- Fujitsu Limited
- Michael G. Peters
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multilayer circuit structure build up method
- Patent number 6,428,942
- Issue date Aug 6, 2002
- Fujitsu Limited
- Hunt Hang Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure of z-connected laminated substrate for high de...
- Patent number 6,326,555
- Issue date Dec 4, 2001
- Fujitsu Limited
- Mark Thomas McCormack
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods for making circuit substrates and electrical assemblies
- Patent number 6,281,040
- Issue date Aug 28, 2001
- Fujitsu Limited
- Mark Thomas McCormack
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor with polymeric layer
- Patent number 6,271,107
- Issue date Aug 7, 2001
- Fujitsu Limited
- Thomas Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer laminated substrates with high density interconnects and...
- Patent number 6,163,957
- Issue date Dec 26, 2000
- Fujitsu Limited
- Hunt Hang Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer circuit substrates and electrical assemblies having con...
- Patent number 6,054,761
- Issue date Apr 25, 2000
- Fujitsu Limited
- Mark Thomas McCormack
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT METALLIC ION DIFFUSION DEFECT VALIDATION
- Publication number 20200243403
- Publication date Jul 30, 2020
- Microsoft Technology Licensing, LLC
- Mark Thomas MCCORMACK
- G01 - MEASURING TESTING
Information Patent Application
Graphic Formation via Material Ablation
- Publication number 20160143170
- Publication date May 19, 2016
- Microsoft Technology Licensing, LLC
- Mark Thomas McCormack
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
ELECTRONIC DEVICE WITH PLATED ELECTRICAL CONTACT
- Publication number 20160048159
- Publication date Feb 18, 2016
- Microsoft Corporation
- Mark Thomas McCormack
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Graphic Formation via Material Ablation
- Publication number 20140248506
- Publication date Sep 4, 2014
- Microsoft Corporation
- Mark Thomas McCormack
- B44 - DECORATIVE ARTS
Information Patent Application
Structure and method of embedding components in multi-layer substrates
- Publication number 20050153060
- Publication date Jul 14, 2005
- Mark Thomas McCormack
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and apparatus for wafer level testing of integrated optical...
- Publication number 20050100266
- Publication date May 12, 2005
- Dmitri E. Nikonov
- G01 - MEASURING TESTING
Information Patent Application
Structure and method for embedding capacitors in z-connected multi-...
- Publication number 20040207042
- Publication date Oct 21, 2004
- Mark Thomas McCormack
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for wafer level testing of integrated optical...
- Publication number 20030123804
- Publication date Jul 3, 2003
- Dmitri E. Nikonov
- G01 - MEASURING TESTING
Information Patent Application
INTERPOSER AND METHOD FOR PRODUCING A LIGHT-GUIDING STRUCTURE
- Publication number 20030103712
- Publication date Jun 5, 2003
- Alexei Glebov
- G02 - OPTICS
Information Patent Application
Structure and method for embedding capacitors in Z-connected multi-...
- Publication number 20030089936
- Publication date May 15, 2003
- Mark Thomas McCormack
- G11 - INFORMATION STORAGE
Information Patent Application
Structure and method of embedding components in multi-layer substrates
- Publication number 20020175402
- Publication date Nov 28, 2002
- Mark Thomas McCormack
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-chip module and method for forming and method for deplating d...
- Publication number 20020155661
- Publication date Oct 24, 2002
- Thomas J. Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method for depositing solder bumps on a wafer
- Publication number 20020151164
- Publication date Oct 17, 2002
- Hunt Hang Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method for forming z-laminated multilayered packaging...
- Publication number 20020119396
- Publication date Aug 29, 2002
- Hunt Hang Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for fabricating flexible circuit structures
- Publication number 20020117256
- Publication date Aug 29, 2002
- Mark Thomas McCormack
- B32 - LAYERED PRODUCTS
Information Patent Application
Methods for detaching a layer from a substrate
- Publication number 20020106522
- Publication date Aug 8, 2002
- Mark Thomas McCormack
- B32 - LAYERED PRODUCTS
Information Patent Application
Method for joining large substrates
- Publication number 20020088540
- Publication date Jul 11, 2002
- Albert W. Chan
- B32 - LAYERED PRODUCTS
Information Patent Application
Composite interposer and method for producing a composite interposer
- Publication number 20020076919
- Publication date Jun 20, 2002
- Michael G. Peters
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Device transfer method
- Publication number 20020036055
- Publication date Mar 28, 2002
- Tetsuzo Yoshimura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Optical coupling structures and the fabrication processes
- Publication number 20020028045
- Publication date Mar 7, 2002
- Tetsuzo Yoshimura
- G02 - OPTICS
Information Patent Application
Conductive composition
- Publication number 20010030062
- Publication date Oct 18, 2001
- Mark Thomas McCormack
- H01 - BASIC ELECTRIC ELEMENTS

Mark Thomas McCormack

Person

Patents Grantslast 30 patents

Integrated circuit metallic ion diffusion defect validation

Graphic formation via material ablation

Electronic device with plated electrical contact

Method of embedding components in multi-layer circuit boards

Method and apparatus for wafer level testing of integrated optical...

Structure and method for embedding capacitors in z-connected multi-...

Multi-chip module and method for forming and method for deplating d...

Method for joining large substrates

Method and apparatus for wafer level testing of integrated optical...

Structure and method for embedding capacitors in z-connected multi-...

Optical coupling structures and the fabrication processes

Device transfer method

Interposer and method for producing a light-guiding structure

Conductive composition

Methods for fabricating flexible circuit structures

Methods for detaching a layer from a substrate

Composite interposer and method for producing a composite interposer

Multilayer circuit structure build up method

Method and structure of z-connected laminated substrate for high de...

Methods for making circuit substrates and electrical assemblies

Semiconductor with polymeric layer

Multilayer laminated substrates with high density interconnects and...

Multi-layer circuit substrates and electrical assemblies having con...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT METALLIC ION DIFFUSION DEFECT VALIDATION

Graphic Formation via Material Ablation

ELECTRONIC DEVICE WITH PLATED ELECTRICAL CONTACT

Graphic Formation via Material Ablation

Structure and method of embedding components in multi-layer substrates

Method and apparatus for wafer level testing of integrated optical...

Structure and method for embedding capacitors in z-connected multi-...

Method and apparatus for wafer level testing of integrated optical...

INTERPOSER AND METHOD FOR PRODUCING A LIGHT-GUIDING STRUCTURE

Structure and method for embedding capacitors in Z-connected multi-...

Structure and method of embedding components in multi-layer substrates

Multi-chip module and method for forming and method for deplating d...

Structure and method for depositing solder bumps on a wafer

Structure and method for forming z-laminated multilayered packaging...

Methods for fabricating flexible circuit structures

Methods for detaching a layer from a substrate

Method for joining large substrates

Composite interposer and method for producing a composite interposer

Device transfer method

Optical coupling structures and the fabrication processes

Conductive composition