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Mark W. Jetton
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Austin, TX, US
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Patents Grants
last 30 patents
Information
Patent Grant
Memory column drowsy control
Patent number
9,317,087
Issue date
Apr 19, 2016
Ravindraraj Ramaraju
Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information
Patent Grant
Bypass system and method that mimics clock to data memory read timing
Patent number
9,263,100
Issue date
Feb 16, 2016
FREESCALE SEMICONDUCTOR, INC.
Bradley J. Garni
G11 - INFORMATION STORAGE
Information
Patent Grant
Memory with word level power gating
Patent number
9,026,808
Issue date
May 5, 2015
FREESCALE SEMICONDUCTOR, INC.
Jianan Yang
G11 - INFORMATION STORAGE
Information
Patent Grant
SRAM with embedded ROM
Patent number
8,995,178
Issue date
Mar 31, 2015
FREESCALE SEMICONDUCTOR, INC.
Jianan Yang
G11 - INFORMATION STORAGE
Information
Patent Grant
Method and apparatus for sensing on-chip characteristics
Patent number
8,766,703
Issue date
Jul 1, 2014
FREESCALE SEMICONDUCTOR, INC.
Jianan Yang
G05 - CONTROLLING REGULATING
Information
Patent Grant
Memory having a dummy bitline for timing control
Patent number
7,746,716
Issue date
Jun 29, 2010
FREESCALE SEMICONDUCTOR, INC.
Mark W. Jetton
G11 - INFORMATION STORAGE
Patents Applications
last 30 patents
Information
Patent Application
BYPASS SYSTEM AND METHOD THAT MIMICS CLOCK TO DATA MEMORY READ TIMING
Publication number
20150155017
Publication date
Jun 4, 2015
FREESCALE SEMICONDUCTOR, INC.
Bradley J. Garni
G11 - INFORMATION STORAGE
Information
Patent Application
MEMORY COLUMN DROWSY CONTROL
Publication number
20130290753
Publication date
Oct 31, 2013
Ravindraraj Ramaraju
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
MEMORY WITH WORD LEVEL POWER GATING
Publication number
20130290750
Publication date
Oct 31, 2013
FREESCALE SEMICONDUCTOR, INC.
Jianan Yang
G11 - INFORMATION STORAGE
Information
Patent Application
MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL
Publication number
20080205176
Publication date
Aug 28, 2008
Mark W. Jetton
G11 - INFORMATION STORAGE