Mark W. Kuemerle

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Lateral escape using triangular structure of transceivers
- Patent number 12,095,494
- Issue date Sep 17, 2024
- MARVELL ASIA PTE. LTD.
- Aatreya Chakravarti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Partitioned substrates with interconnect bridge
- Patent number 11,282,806
- Issue date Mar 22, 2022
- Marvell Asia Pte, Ltd.
- Wolfgang Sauter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hermetic barrier for semiconductor device
- Patent number 11,037,873
- Issue date Jun 15, 2021
- MARVELL GOVERNMENT SOLUTIONS, LLC.
- Nicholas A. Polomoff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip module (MCM) with chip-to-chip connection redundancy and...
- Patent number 10,748,852
- Issue date Aug 18, 2020
- Marvell International Ltd.
- Wolfgang Sauter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnected integrated circuit (IC) chip structure and packaging...
- Patent number 10,714,411
- Issue date Jul 14, 2020
- GLOBALFOUNDRIES Inc.
- Wolfgang Sauter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure
- Patent number 10,381,304
- Issue date Aug 13, 2019
- GLOBALFOUNDRIES Inc.
- Luke England
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated interface structure
- Patent number 9,875,956
- Issue date Jan 23, 2018
- GLOBALFOUNDRIES Inc.
- Wolfgang Sauter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double bandwidth algorithmic memory array
- Patent number 9,870,163
- Issue date Jan 16, 2018
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing/power risk optimized selective voltage binning using non-lin...
- Patent number 9,865,486
- Issue date Jan 9, 2018
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip design methods and systems using process wi...
- Patent number 9,619,609
- Issue date Apr 11, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for controlling integrated circuit chip tempera...
- Patent number 9,552,447
- Issue date Jan 24, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Composite views for IP blocks in ASIC designs
- Patent number 9,501,607
- Issue date Nov 22, 2016
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reverse performance binning
- Patent number 9,372,520
- Issue date Jun 21, 2016
- GLOBALFOUNDRIES Inc.
- Mark W. Kuemerle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for managing circuit performance and power consum...
- Patent number 9,269,407
- Issue date Feb 23, 2016
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G11 - INFORMATION STORAGE
Information Patent Grant
Limiting skew between different device types to meet performance re...
- Patent number 9,171,125
- Issue date Oct 27, 2015
- GlobalFoundries U.S. 2 LLC
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling circuit voltage and frequency based upon location-depen...
- Patent number 8,963,620
- Issue date Feb 24, 2015
- International Business Machines Corporation
- Jeanne P. S. Bickford
- G05 - CONTROLLING REGULATING
Information Patent Grant
Power and timing optimization for an integrated circuit by voltage...
- Patent number 8,843,874
- Issue date Sep 23, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Power/performance optimization through continuously variable temper...
- Patent number 8,839,165
- Issue date Sep 16, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power/performance optimization through temperature/voltage control
- Patent number 8,839,170
- Issue date Sep 16, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Power and timing optimization for an integrated circuit by voltage...
- Patent number 8,543,960
- Issue date Sep 24, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Method, circuit, and design structure for capturing data across a p...
- Patent number 8,300,752
- Issue date Oct 30, 2012
- International Business Machines Corporation
- Malede W. Berhanu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method, circuit, and design structure for capturing data across a p...
- Patent number 8,189,723
- Issue date May 29, 2012
- International Business Machines Corporation
- Malede W. Berhanu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System for expanding a window of valid data
- Patent number 7,529,962
- Issue date May 5, 2009
- International Business Machines Corporation
- Malede Wondmagegne Berhanu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit design closure method for selective voltage binning
- Patent number 7,475,366
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Mark W. Kuemerle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for power optimization in parallel units
- Patent number 6,457,131
- Issue date Sep 24, 2002
- International Business Machines Corporation
- Mark William Kuemerle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for power optimization in parallel units
- Patent number 6,289,465
- Issue date Sep 11, 2001
- International Business Machines Corporation
- Mark William Kuemerle
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Lateral escape using triangular structure of transceivers
- Publication number 20240405795
- Publication date Dec 5, 2024
- Marvell Asia Pte Ltd.
- Aatreya Chakravarti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH STACKED INTERFACE CHIPLETS
- Publication number 20240258272
- Publication date Aug 1, 2024
- Marvell Asia Pte Ltd.
- Aatreya Chakravarti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARTITIONED SUBSTRATES WITH INTERCONNECT BRIDGE
- Publication number 20210111141
- Publication date Apr 15, 2021
- GLOBALFOUNDRIES INC.
- Wolfgang SAUTER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HERMETIC BARRIER FOR SEMICONDUCTOR DEVICE
- Publication number 20200381355
- Publication date Dec 3, 2020
- Avera Semiconductor LLC
- Nicholas A. Polomoff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING...
- Publication number 20190287879
- Publication date Sep 19, 2019
- GLOBALFOUNDRIES INC.
- Wolfgang Sauter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE
- Publication number 20190035731
- Publication date Jan 31, 2019
- GLOBALFOUNDRIES INC.
- Luke ENGLAND
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY
- Publication number 20170315738
- Publication date Nov 2, 2017
- GLOBALFOUNDRIES INC.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING/POWER RISK OPTIMIZED SELECTIVE VOLTAGE BINNING USING NON-LIN...
- Publication number 20170287756
- Publication date Oct 5, 2017
- GLOBALFOUNDRIES INC.
- IGOR ARSOVSKI
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WI...
- Publication number 20170083661
- Publication date Mar 23, 2017
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPOSITE VIEWS FOR IP BLOCKS IN ASIC DESIGNS
- Publication number 20160364516
- Publication date Dec 15, 2016
- International Business Machines Corporation
- Igor ARSOVSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERA...
- Publication number 20160314229
- Publication date Oct 27, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIMITING SKEW BETWEEN DIFFERENT DEVICE TYPES TO MEET PERFORMANCE RE...
- Publication number 20150242560
- Publication date Aug 27, 2015
- International Business Machines Corporation
- Igor ARSOVSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REVERSE PERFORMANCE BINNING
- Publication number 20150046739
- Publication date Feb 12, 2015
- International Business Machines Corporation
- Mark W. Kuemerle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING CIRCUIT VOLTAGE AND FREQUENCY BASED UPON LOCATION-DEPEN...
- Publication number 20150028937
- Publication date Jan 29, 2015
- International Business Machines Corporation
- Jean P.S. Bickford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STATISTICAL POWER ESTIMATION
- Publication number 20150025857
- Publication date Jan 22, 2015
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER/PERFORMANCE OPTIMIZATION THROUGH CONTINUOUSLY VARIABLE TEMPER...
- Publication number 20140215429
- Publication date Jul 31, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL
- Publication number 20130326459
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
POWER AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT BY VOLTAGE...
- Publication number 20130326460
- Publication date Dec 5, 2013
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A P...
- Publication number 20100039150
- Publication date Feb 18, 2010
- Malede W. Berhanu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A P...
- Publication number 20100040183
- Publication date Feb 18, 2010
- Malede W. Berhanu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTEGRATED CIRCUIT DESIGN CLOSURE METHOD FOR SELECTIVE VOLTAGE BINNING
- Publication number 20080034337
- Publication date Feb 7, 2008
- Mark W. Kuemerle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for power optimization in parallel units
- Publication number 20020002664
- Publication date Jan 3, 2002
- International Business Machines Corporation
- Mark William Kuemerle
- G06 - COMPUTING CALCULATING COUNTING

Mark W. Kuemerle

Person

Patents Grantslast 30 patents

Lateral escape using triangular structure of transceivers

Partitioned substrates with interconnect bridge

Hermetic barrier for semiconductor device

Multi-chip module (MCM) with chip-to-chip connection redundancy and...

Interconnected integrated circuit (IC) chip structure and packaging...

Interconnect structure

Integrated interface structure

Double bandwidth algorithmic memory array

Timing/power risk optimized selective voltage binning using non-lin...

Integrated circuit chip design methods and systems using process wi...

Systems and methods for controlling integrated circuit chip tempera...

Composite views for IP blocks in ASIC designs

Reverse performance binning

System and method for managing circuit performance and power consum...

Limiting skew between different device types to meet performance re...

Controlling circuit voltage and frequency based upon location-depen...

Power and timing optimization for an integrated circuit by voltage...

Power/performance optimization through continuously variable temper...

Power/performance optimization through temperature/voltage control

Power and timing optimization for an integrated circuit by voltage...

Method, circuit, and design structure for capturing data across a p...

Method, circuit, and design structure for capturing data across a p...

System for expanding a window of valid data

Integrated circuit design closure method for selective voltage binning

System and method for power optimization in parallel units

System and method for power optimization in parallel units

Patents Applicationslast 30 patents

Lateral escape using triangular structure of transceivers

INTEGRATED CIRCUIT DEVICE WITH STACKED INTERFACE CHIPLETS

PARTITIONED SUBSTRATES WITH INTERCONNECT BRIDGE

HERMETIC BARRIER FOR SEMICONDUCTOR DEVICE

INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING...

INTERCONNECT STRUCTURE

DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY

TIMING/POWER RISK OPTIMIZED SELECTIVE VOLTAGE BINNING USING NON-LIN...

INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WI...

COMPOSITE VIEWS FOR IP BLOCKS IN ASIC DESIGNS

SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERA...

LIMITING SKEW BETWEEN DIFFERENT DEVICE TYPES TO MEET PERFORMANCE RE...

REVERSE PERFORMANCE BINNING

CONTROLLING CIRCUIT VOLTAGE AND FREQUENCY BASED UPON LOCATION-DEPEN...

STATISTICAL POWER ESTIMATION

POWER/PERFORMANCE OPTIMIZATION THROUGH CONTINUOUSLY VARIABLE TEMPER...

POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL

POWER AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT BY VOLTAGE...

METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A P...

METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A P...

INTEGRATED CIRCUIT DESIGN CLOSURE METHOD FOR SELECTIVE VOLTAGE BINNING

System and method for power optimization in parallel units