Mark W. McDermott

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Nanoscale-aligned three-dimensional stacked integrated circuit
- Patent number 12,094,775
- Issue date Sep 17, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanofabrication and design techniques for 3D ICs and configurable A...
- Patent number 12,079,557
- Issue date Sep 3, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous integration of components onto compact devices using...
- Patent number 12,009,247
- Issue date Jun 11, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Nanoscale-aligned three-dimensional stacked integrated circuit
- Patent number 11,600,525
- Issue date Mar 7, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous integration of components onto compact devices using...
- Patent number 11,469,131
- Issue date Oct 11, 2022
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Selectable clock generation mode
- Patent number 5,926,053
- Issue date Jul 20, 1999
- National Semiconductor Corporation
- Mark W. McDermott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NDIRTY cache line lookahead
- Patent number 5,860,105
- Issue date Jan 12, 1999
- National Semiconductor Corporation
- Mark W. McDermott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed clock generator
- Patent number 5,815,692
- Issue date Sep 29, 1998
- National Semiconductor Corporation
- Mark W. McDermott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having a frequency modulated core clock based on the crit...
- Patent number 5,815,693
- Issue date Sep 29, 1998
- National Semiconductor Corporation
- Mark W. McDermott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static clock generator
- Patent number 5,740,410
- Issue date Apr 14, 1998
- Cyrix Corporation
- Mark W. McDermott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bidirectional single-line handshake with both devices driving the l...
- Patent number 5,734,844
- Issue date Mar 31, 1998
- Cyrix Corporation
- Claude Moughanni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting short branches in a prefetch buffer using target location...
- Patent number 5,734,881
- Issue date Mar 31, 1998
- Cyrix Corporation
- Christopher E. White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable NAND/NOR element
- Patent number 5,592,107
- Issue date Jan 7, 1997
- Cyrix Corporation
- Mark W. McDermott
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable XNOR/XOR element
- Patent number 5,568,067
- Issue date Oct 22, 1996
- Cyrix Corporation
- Mark W. McDermott
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit microprocessor with programmable chip select logic
- Patent number 5,448,744
- Issue date Sep 5, 1995
- Motorola, Inc.
- James B. Eifert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to accelerate counter testing without loss of fault coverage
- Patent number 5,402,458
- Issue date Mar 28, 1995
- Cyrix Corporation
- Claude Moughanni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital computing system with low power mode and special bus cycle...
- Patent number 5,361,392
- Issue date Nov 1, 1994
- Motorola, Inc.
- Antone L. Fourcroy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated charge-pump phase-locked loop circuit
- Patent number 5,233,314
- Issue date Aug 3, 1993
- Cyrix Corporation
- Mark W. McDermott
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data processor test architecture
- Patent number 5,157,781
- Issue date Oct 20, 1992
- Motorola, Inc.
- Wallace B. Harwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spurious interrupt monitor
- Patent number 5,138,709
- Issue date Aug 11, 1992
- Motorola, Inc.
- Randall L. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output circuit with programmable input sensing time
- Patent number 5,029,272
- Issue date Jul 2, 1991
- Motorola, Inc.
- Antone L. Fourcroy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
MOS output buffer with reduced supply line disturbance
- Patent number 4,959,561
- Issue date Sep 25, 1990
- Motorola, Inc.
- Mark W. McDermott
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with clock generator
- Patent number 4,931,748
- Issue date Jun 5, 1990
- Motorola, Inc.
- Mark W. McDermott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power down detector
- Patent number 4,366,560
- Issue date Dec 28, 1982
- Motorola, Inc.
- Mark W. McDermott
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT
- Publication number 20240429099
- Publication date Dec 26, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING...
- Publication number 20240332056
- Publication date Oct 3, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20230419010
- Publication date Dec 28, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20230124676
- Publication date Apr 20, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20230118578
- Publication date Apr 20, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT
- Publication number 20230116581
- Publication date Apr 13, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING...
- Publication number 20230042873
- Publication date Feb 9, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT
- Publication number 20210366771
- Publication date Nov 25, 2021
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20210350061
- Publication date Nov 11, 2021
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING...
- Publication number 20210134640
- Publication date May 6, 2021
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- B81 - MICRO-STRUCTURAL TECHNOLOGY

Mark W. McDermott

Person

Patents Grantslast 30 patents

Nanoscale-aligned three-dimensional stacked integrated circuit

Nanofabrication and design techniques for 3D ICs and configurable A...

Heterogeneous integration of components onto compact devices using...

Nanoscale-aligned three-dimensional stacked integrated circuit

Heterogeneous integration of components onto compact devices using...

Selectable clock generation mode

NDIRTY cache line lookahead

Distributed clock generator

Processor having a frequency modulated core clock based on the crit...

Static clock generator

Bidirectional single-line handshake with both devices driving the l...

Detecting short branches in a prefetch buffer using target location...

Configurable NAND/NOR element

Configurable XNOR/XOR element

Integrated circuit microprocessor with programmable chip select logic

Mechanism to accelerate counter testing without loss of fault coverage

Digital computing system with low power mode and special bus cycle...

Integrated charge-pump phase-locked loop circuit

Data processor test architecture

Spurious interrupt monitor

Input/output circuit with programmable input sensing time

MOS output buffer with reduced supply line disturbance

Integrated circuit with clock generator

Power down detector

Patents Applicationslast 30 patents

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING...

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING...

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING...