Martin J. Schwartz

Person

Worcester, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Tester with fast refire recovery time
- Patent number 5,854,797
- Issue date Dec 29, 1998
- Teradyne, Inc.
- Martin J. Schwartz
- G01 - MEASURING TESTING
Information Patent Grant
CPU having pipelined instruction unit and effective address calcula...
- Patent number 5,404,467
- Issue date Apr 4, 1995
- Wang Laboratories, Inc.
- John A. Saba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory control unit with selective execution of queued read and wri...
- Patent number 5,379,379
- Issue date Jan 3, 1995
- Wang Laboratories, Inc.
- Robert D. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System bus having multiplexed command/ID and data
- Patent number 5,235,684
- Issue date Aug 10, 1993
- Wang Laboratories, Inc.
- Robert D. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor system with cache memories
- Patent number 5,097,409
- Issue date Mar 17, 1992
- Wang Laboratories, Inc.
- Martin J. Schwartz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for executing a conditional branch instruction
- Patent number 5,034,880
- Issue date Jul 23, 1991
- Wang Laboratories, Inc.
- Anthony S. Fong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory diagnostic apparatus and method
- Patent number 4,943,966
- Issue date Jul 24, 1990
- Wang Laboratories, Inc.
- Richard F. Giunta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor system with cache memories
- Patent number 4,939,641
- Issue date Jul 3, 1990
- Wang Laboratories, Inc.
- Martin J. Schwartz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Byte addressable memory for variable length instructions and data
- Patent number 4,654,781
- Issue date Mar 31, 1987
- Raytheon Company
- Martin J. Schwartz
- G06 - COMPUTING CALCULATING COUNTING

Martin J. Schwartz

Person

Patents Grantslast 30 patents

Tester with fast refire recovery time

CPU having pipelined instruction unit and effective address calcula...

Memory control unit with selective execution of queued read and wri...

System bus having multiplexed command/ID and data

Multi-processor system with cache memories

Apparatus and method for executing a conditional branch instruction

Memory diagnostic apparatus and method

Multi-processor system with cache memories

Byte addressable memory for variable length instructions and data