Martin M. MITAN

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned gate endcap (SAGE) architectures without fin end gap
- Patent number 11,869,889
- Issue date Jan 9, 2024
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel formation for three dimensional transistors
- Patent number 11,810,980
- Issue date Nov 7, 2023
- Intel Corporation
- Chieh-Jen Ku
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective gate spacers for semiconductor devices
- Patent number 11,532,724
- Issue date Dec 20, 2022
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of multi-channel nanowire devices with self-aligned int...
- Patent number 10,998,423
- Issue date May 4, 2021
- Intel Corporation
- Van H. Le
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Selective gate spacers for semiconductor devices
- Patent number 10,971,600
- Issue date Apr 6, 2021
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for doping a sub-fin region of a semiconductor fin structur...
- Patent number 10,896,852
- Issue date Jan 19, 2021
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of multi-channel nanowire devices with self-aligned int...
- Patent number 10,720,508
- Issue date Jul 21, 2020
- Intel Corporation
- Van H. Le
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Selective gate spacers for semiconductor devices
- Patent number 10,396,176
- Issue date Aug 27, 2019
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
- Publication number 20240088143
- Publication date Mar 14, 2024
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES
- Publication number 20210143265
- Publication date May 13, 2021
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
- Publication number 20210091075
- Publication date Mar 25, 2021
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL FORMATION FOR THREE DIMENSIONAL TRANSISTORS
- Publication number 20200411697
- Publication date Dec 31, 2020
- Intel Corporation
- Chieh-Jen KU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF MULTI-CHANNEL NANOWIRE DEVICES WITH SELF-ALIGNED INT...
- Publication number 20200287022
- Publication date Sep 10, 2020
- Intel Corporation
- Van H. LE
- B82 - NANO-TECHNOLOGY
Information Patent Application
SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES
- Publication number 20200020786
- Publication date Jan 16, 2020
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF MULTI-CHANNEL NANOWIRE DEVICES WITH SELF-ALIGNED INT...
- Publication number 20180226490
- Publication date Aug 9, 2018
- Intel Corporation
- Van H. LE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES
- Publication number 20180219080
- Publication date Aug 2, 2018
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES
- Publication number 20180130707
- Publication date May 10, 2018
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS

Martin M. MITAN

Person

Patents Grantslast 30 patents

Self-aligned gate endcap (SAGE) architectures without fin end gap

Channel formation for three dimensional transistors

Selective gate spacers for semiconductor devices

Fabrication of multi-channel nanowire devices with self-aligned int...

Selective gate spacers for semiconductor devices

Methods for doping a sub-fin region of a semiconductor fin structur...

Fabrication of multi-channel nanowire devices with self-aligned int...

Selective gate spacers for semiconductor devices

Patents Applicationslast 30 patents

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP

CHANNEL FORMATION FOR THREE DIMENSIONAL TRANSISTORS

FABRICATION OF MULTI-CHANNEL NANOWIRE DEVICES WITH SELF-ALIGNED INT...

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

FABRICATION OF MULTI-CHANNEL NANOWIRE DEVICES WITH SELF-ALIGNED INT...

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES