Martin Thomas Mason

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enhanced board level reliability for wafer level packages
- Patent number 9,837,368
- Issue date Dec 5, 2017
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable mixed-signal input/output (IO)
- Patent number 9,525,420
- Issue date Dec 20, 2016
- Maxim Integrated Products, Inc.
- Arman Hematy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable multichannel signal selector
- Patent number 9,479,188
- Issue date Oct 25, 2016
- Maxim Integrated Products, Inc.
- Martin T. Mason
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable mixed-signal input/output (IO)
- Patent number 9,148,147
- Issue date Sep 29, 2015
- Maxim Integrated Products, Inc.
- Arman Hematy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable gate array including a non-volatile user memory...
- Patent number 7,919,979
- Issue date Apr 5, 2011
- Actel Corporation
- Martin Mason
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for implementing a physical design for a dynamically reconfi...
- Patent number 6,678,646
- Issue date Jan 13, 2004
- Atmel Corporation
- David A. McConnell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure programmable logic device
- Patent number 6,331,784
- Issue date Dec 18, 2001
- Atmel Corporation
- Martin T. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA structure having main, column and sector reset lines
- Patent number 6,292,021
- Issue date Sep 18, 2001
- Atmel Corporation
- Frederick C. Furtek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Software tool to allow field programmable system level devices
- Patent number 6,272,451
- Issue date Aug 7, 2001
- Atmel Corporation
- Martin Thomas Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA structure having main, column and sector clock lines
- Patent number 6,167,559
- Issue date Dec 26, 2000
- Atmel Corporation
- Frederick C. Furtek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA logic cell internal structure including pair of look-up tables
- Patent number 6,026,227
- Issue date Feb 15, 2000
- Atmel Corporation
- Frederick C. Furtek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable gate array having access to orthogonal and diago...
- Patent number 6,014,509
- Issue date Jan 11, 2000
- Atmel Corporation
- Frederick C. Furtek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Motor control apparatus
- Patent number 5,990,640
- Issue date Nov 23, 1999
- Aim Controls, Inc.
- Patrick H. Dwyer
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method and system for configuring an array of logic devices
- Patent number 5,946,219
- Issue date Aug 31, 1999
- Atmel Corporation
- Martin T. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array with distributed RAM and increased ce...
- Patent number 5,894,565
- Issue date Apr 13, 1999
- Atmel Corporation
- Frederick C. Furtek
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE MIXED-SIGNAL INPUT/OUTPUT (IO)
- Publication number 20160020770
- Publication date Jan 21, 2016
- Maxim Integrated Products, Inc.
- Arman Hematy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ENHANCED BOARD LEVEL RELIABILITY FOR WAFER LEVEL PACKAGES
- Publication number 20150255413
- Publication date Sep 10, 2015
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Programmable mixed-signal input/output (IO)
- Publication number 20140354328
- Publication date Dec 4, 2014
- Maxim Integrated Products, Inc.
- Arman Hematy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NONVOLATILE USER MEMORY A...
- Publication number 20090058462
- Publication date Mar 5, 2009
- Actel Corporation
- Martin Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Software tool to allow field programmable system level devices
- Publication number 20010049593
- Publication date Dec 6, 2001
- David Andrew Mc Connell
- G06 - COMPUTING CALCULATING COUNTING

Martin Thomas Mason

Person

Patents Grantslast 30 patents

Enhanced board level reliability for wafer level packages

Programmable mixed-signal input/output (IO)

Programmable multichannel signal selector

Programmable mixed-signal input/output (IO)

Field programmable gate array including a non-volatile user memory...

Method for implementing a physical design for a dynamically reconfi...

Secure programmable logic device

FPGA structure having main, column and sector reset lines

Software tool to allow field programmable system level devices

FPGA structure having main, column and sector clock lines

FPGA logic cell internal structure including pair of look-up tables

Field programmable gate array having access to orthogonal and diago...

Motor control apparatus

Method and system for configuring an array of logic devices

Field programmable gate array with distributed RAM and increased ce...

Patents Applicationslast 30 patents

PROGRAMMABLE MIXED-SIGNAL INPUT/OUTPUT (IO)

ENHANCED BOARD LEVEL RELIABILITY FOR WAFER LEVEL PACKAGES

Programmable mixed-signal input/output (IO)

FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NONVOLATILE USER MEMORY A...

Software tool to allow field programmable system level devices