Martin Vorbach

Person

Karlsruhe, DE

People

Patents Grantslast 30 patents

Information Patent Grant
High performance processor
- Patent number 11,797,474
- Issue date Oct 24, 2023
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing code sections for matrix of arithmetic logic units in a p...
- Patent number 11,687,346
- Issue date Jun 27, 2023
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced processor architecture
- Patent number 11,061,682
- Issue date Jul 13, 2021
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Issuing instructions to multiple execution units
- Patent number 10,908,914
- Issue date Feb 2, 2021
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having a programmable function unit
- Patent number 10,885,996
- Issue date Jan 5, 2021
- PACT XPP SCHWEIZ AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated data processing core and array data processor and method...
- Patent number 10,579,584
- Issue date Mar 3, 2020
- PACT XPP SCHWEIZ AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Issuing instructions to multiple execution units
- Patent number 10,409,608
- Issue date Sep 10, 2019
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for providing subapplications to an array of ALUs
- Patent number 10,409,765
- Issue date Sep 10, 2019
- PACT XPP SCHWEIZ AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and devices for treating and processing data
- Patent number 10,331,194
- Issue date Jun 25, 2019
- PACT XPP SCHWEIZ AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of loops and data flow sections in multi-core processo...
- Patent number 10,331,615
- Issue date Jun 25, 2019
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor with selectively interconnected memory units
- Patent number 10,296,488
- Issue date May 21, 2019
- PACT XPP SCHWEIZ AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of transferring data between external devices and an array p...
- Patent number 10,152,320
- Issue date Dec 11, 2018
- Scientia Sol Mentis AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel memory systems
- Patent number 10,031,888
- Issue date Jul 24, 2018
- Hyperion Core, Inc.
- Martin Vorbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for processing data
- Patent number 10,031,733
- Issue date Jul 24, 2018
- Scientia Sol Mentis AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Issuing instructions to multiple execution units
- Patent number 9,898,297
- Issue date Feb 20, 2018
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor with selectively interconnected memory units
- Patent number 9,817,790
- Issue date Nov 14, 2017
- Pact XPP Technologies AG
- Martin Vorbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for a cache in a multi-core processor
- Patent number 9,734,064
- Issue date Aug 15, 2017
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tool-level and hardware-level code optimization and respective hard...
- Patent number 9,703,538
- Issue date Jul 11, 2017
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic integrated circuit having a multidimensional str...
- Patent number 9,690,747
- Issue date Jun 27, 2017
- PACT XPP Technologies, AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of loops and data flow sections in multi-core processo...
- Patent number 9,672,188
- Issue date Jun 6, 2017
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array processor having a segmented bus system
- Patent number 9,626,325
- Issue date Apr 18, 2017
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor having runtime adjustable clock and clock dependent...
- Patent number 9,552,047
- Issue date Jan 24, 2017
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip including memory element storing higher level memory data on a...
- Patent number 9,436,631
- Issue date Sep 6, 2016
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for transferring data between a processing devi...
- Patent number 9,411,532
- Issue date Aug 9, 2016
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing code sections for matrix of arithmetic logic units in a p...
- Patent number 9,348,587
- Issue date May 24, 2016
- Hyperion Core, Inc.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor with selectively interconnected memory units
- Patent number 9,274,984
- Issue date Mar 1, 2016
- Pact XPP Technologies AG
- Martin Vorbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data processor chip with flexible bus system
- Patent number 9,256,575
- Issue date Feb 9, 2016
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor bus and cache interconnection system
- Patent number 9,250,908
- Issue date Feb 2, 2016
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked-die multi-processor
- Patent number 9,240,220
- Issue date Jan 19, 2016
- Pact XPP Technologies AG
- Martin Vorbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Data processing system having integrated pipelined array data proce...
- Patent number 9,170,812
- Issue date Oct 27, 2015
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIGH PERFORMANCE PROCESSOR
- Publication number 20240054097
- Publication date Feb 15, 2024
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...
- Publication number 20230409334
- Publication date Dec 21, 2023
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED PROCESSOR ARCHITECTURE
- Publication number 20210406027
- Publication date Dec 30, 2021
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE PROCESSOR
- Publication number 20210286755
- Publication date Sep 16, 2021
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...
- Publication number 20210026637
- Publication date Jan 28, 2021
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS
- Publication number 20200241879
- Publication date Jul 30, 2020
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PROVIDING SUBAPPLICATIONS TO AN ARRAY OF ALUS
- Publication number 20200057749
- Publication date Feb 20, 2020
- Scientia Sol Mentis AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF LOOPS AND DATA FLOW SECTIONS IN MULTI-CORE PROCESSO...
- Publication number 20200042492
- Publication date Feb 6, 2020
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTION OF INSTRUCTIONS BASED ON PROCESSOR AND DATA AVAILABILITY
- Publication number 20190377580
- Publication date Dec 12, 2019
- HYPERION CORE INC.
- Martin VORBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL MEMORY SYSTEMS
- Publication number 20190197015
- Publication date Jun 27, 2019
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARD...
- Publication number 20190171449
- Publication date Jun 6, 2019
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR TRANSFERRING DATA BETWEEN A PROCESSING DEVI...
- Publication number 20190102173
- Publication date Apr 4, 2019
- Scientia Sol Mentis AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...
- Publication number 20190079769
- Publication date Mar 14, 2019
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Array Processor Having a Segmented Bus System
- Publication number 20190065428
- Publication date Feb 28, 2019
- Scientia Sol Mentis AG
- Martin VORBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Array Processor Having a Segmented Bus System
- Publication number 20180300278
- Publication date Oct 18, 2018
- PACT XPP TECHNOLOGIES AG
- Martin VORBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS
- Publication number 20180181403
- Publication date Jun 28, 2018
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR WITH SELECTIVELY INTERCONNECTED MEMORY UNITS
- Publication number 20180067896
- Publication date Mar 8, 2018
- PACT XPP TECHNOLOGIES AG
- Martin VORBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR A CACHE IN A MULTI-CORE PROCESSOR
- Publication number 20180039576
- Publication date Feb 8, 2018
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED PROCESSOR ARCHITECTURE
- Publication number 20180004530
- Publication date Jan 4, 2018
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARD...
- Publication number 20170364338
- Publication date Dec 21, 2017
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PROVIDING SUBAPPLICATIONS TO AN ARRAY OF ALUS
- Publication number 20170286364
- Publication date Oct 5, 2017
- PACT XPP TECHNOLOGIES AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF LOOPS AND DATA FLOW SECTIONS IN MULTI-CORE PROCESSO...
- Publication number 20170262406
- Publication date Sep 14, 2017
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and devices for treating and processing data
- Publication number 20170192481
- Publication date Jul 6, 2017
- PACT XPP TECHNOLOGIES AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Transferring Data between External Devices and an Array P...
- Publication number 20160357555
- Publication date Dec 8, 2016
- PACT XPP TECHNOLOGIES AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...
- Publication number 20160306631
- Publication date Oct 20, 2016
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-processor with selectively interconnected memory units
- Publication number 20160170925
- Publication date Jun 16, 2016
- PACT XPP TECHNOLOGIES AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Array Processor Having a Segmented Bus System
- Publication number 20160154758
- Publication date Jun 2, 2016
- PACT XPP TECHNOLOGIES AG
- Martin VORBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Having a Programmable Function Unit
- Publication number 20160141050
- Publication date May 19, 2016
- PACT XPP TECHNOLOGIES AG
- Martin Vorbach
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated data processing core and array data processor and method...
- Publication number 20160055120
- Publication date Feb 25, 2016
- PACT XPP TECHNOLOGIES AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS
- Publication number 20160048394
- Publication date Feb 18, 2016
- HYPERION CORE, INC.
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING

Martin Vorbach

Person

Patents Grantslast 30 patents

High performance processor

Providing code sections for matrix of arithmetic logic units in a p...

Advanced processor architecture

Issuing instructions to multiple execution units

Processor having a programmable function unit

Integrated data processing core and array data processor and method...

Issuing instructions to multiple execution units

Method for providing subapplications to an array of ALUs

Methods and devices for treating and processing data

Optimization of loops and data flow sections in multi-core processo...

Multi-processor with selectively interconnected memory units

Method of transferring data between external devices and an array p...

Parallel memory systems

Method for processing data

Issuing instructions to multiple execution units

Multi-processor with selectively interconnected memory units

System and method for a cache in a multi-core processor

Tool-level and hardware-level code optimization and respective hard...

Configurable logic integrated circuit having a multidimensional str...

Optimization of loops and data flow sections in multi-core processo...

Array processor having a segmented bus system

Multiprocessor having runtime adjustable clock and clock dependent...

Chip including memory element storing higher level memory data on a...

Methods and systems for transferring data between a processing devi...

Providing code sections for matrix of arithmetic logic units in a p...

Multi-processor with selectively interconnected memory units

Data processor chip with flexible bus system

Multi-processor bus and cache interconnection system

Stacked-die multi-processor

Data processing system having integrated pipelined array data proce...

Patents Applicationslast 30 patents

HIGH PERFORMANCE PROCESSOR

PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...

ADVANCED PROCESSOR ARCHITECTURE

HIGH PERFORMANCE PROCESSOR

PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...

ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS

METHOD FOR PROVIDING SUBAPPLICATIONS TO AN ARRAY OF ALUS

OPTIMIZATION OF LOOPS AND DATA FLOW SECTIONS IN MULTI-CORE PROCESSO...

EXECUTION OF INSTRUCTIONS BASED ON PROCESSOR AND DATA AVAILABILITY

PARALLEL MEMORY SYSTEMS

TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARD...

METHODS AND SYSTEMS FOR TRANSFERRING DATA BETWEEN A PROCESSING DEVI...

PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...

Array Processor Having a Segmented Bus System

Array Processor Having a Segmented Bus System

ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS

MULTI-PROCESSOR WITH SELECTIVELY INTERCONNECTED MEMORY UNITS

SYSTEM AND METHOD FOR A CACHE IN A MULTI-CORE PROCESSOR

ADVANCED PROCESSOR ARCHITECTURE

TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARD...

METHOD FOR PROVIDING SUBAPPLICATIONS TO AN ARRAY OF ALUS

OPTIMIZATION OF LOOPS AND DATA FLOW SECTIONS IN MULTI-CORE PROCESSO...

Methods and devices for treating and processing data

Method of Transferring Data between External Devices and an Array P...

PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...

Multi-processor with selectively interconnected memory units

Array Processor Having a Segmented Bus System

Processor Having a Programmable Function Unit

Integrated data processing core and array data processor and method...

ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS