Masaki Oiso

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Tokyo, JP

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor LSI circuit with scan circuit, scan circuit system, s...
- Patent number 7,188,288
- Issue date Mar 6, 2007
- Kabushiki Kaisha Toshiba
- Masaki Oiso
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor integrated circuit detecting glitch noise and test me...
- Patent number 7,139,952
- Issue date Nov 21, 2006
- Kabushiki Kaisha Toshiba
- Takashi Matsumoto
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT, SCAN SHIFT CONTROL METHOD, AND CIRCUIT DESIGN M...
- Publication number 20190080039
- Publication date Mar 14, 2019
- Kabushiki Kaisha Toshiba
- Masaki OISO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit detecting glitch noise and test me...
- Publication number 20050193300
- Publication date Sep 1, 2005
- Takashi Matsumoto
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor LSI circuit with scan circuit, scan circuit system, s...
- Publication number 20050160336
- Publication date Jul 21, 2005
- Masaki Oiso
- G01 - MEASURING TESTING