Masami Murakata

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Noise suppression circuit, ASIC, navigation apparatus, communicatio...
- Patent number 7,230,554
- Issue date Jun 12, 2007
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for distributing clock signals to flip-flop circuits
- Patent number 7,075,336
- Issue date Jul 11, 2006
- Kabushiki Kaisha Toshiba
- Naohito Kojima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise suppression circuit, ASIC, navigation apparatus, communicatio...
- Patent number 7,064,691
- Issue date Jun 20, 2006
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of automatic layout design for LSI, mask set and semiconduct...
- Patent number 6,813,756
- Issue date Nov 2, 2004
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,645,842
- Issue date Nov 11, 2003
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of automatic layout design for LSI, mask set and semiconduct...
- Patent number 6,546,540
- Issue date Apr 8, 2003
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise suppression circuit, ASIC, navigation apparatus communication...
- Patent number 6,459,331
- Issue date Oct 1, 2002
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,436,804
- Issue date Aug 20, 2002
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,262,487
- Issue date Jul 17, 2001
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit and power supply routing method an...
- Patent number 6,118,334
- Issue date Sep 12, 2000
- Kabushiki Kaisha Toshiba
- Hiroshi Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic placement method for arranging logic cells
- Patent number 5,140,402
- Issue date Aug 18, 1992
- Kabushiki Kaisha Toshiba
- Masami Murakata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic cell-layout arranging method and apparatus for polycell l...
- Patent number 4,839,821
- Issue date Jun 13, 1989
- Kabushiki Kaisha Toshiba
- Masami Murakata
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Noise suppression circuit, ASIC, navigation apparatus, communicatio...
- Publication number 20060197695
- Publication date Sep 7, 2006
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of automatic layout design for LSI, mask set and semiconduct...
- Publication number 20030079194
- Publication date Apr 24, 2003
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Noise suppression circuit, asic, navigation apparatus, communicatio...
- Publication number 20030011500
- Publication date Jan 16, 2003
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for distributing clock signals to flip-flop circuits
- Publication number 20030014724
- Publication date Jan 16, 2003
- Naohito Kojima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit device, semiconductor integrated c...
- Publication number 20020182844
- Publication date Dec 5, 2002
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor integrated circuit device, semiconductor integrated c...
- Publication number 20010011776
- Publication date Aug 9, 2001
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS

Masami Murakata

Person

Patents Grantslast 30 patents

Noise suppression circuit, ASIC, navigation apparatus, communicatio...

Method for distributing clock signals to flip-flop circuits

Noise suppression circuit, ASIC, navigation apparatus, communicatio...

Method of automatic layout design for LSI, mask set and semiconduct...

Semiconductor integrated circuit device, semiconductor integrated c...

Method of automatic layout design for LSI, mask set and semiconduct...

Noise suppression circuit, ASIC, navigation apparatus communication...

Semiconductor integrated circuit device, semiconductor integrated c...

Semiconductor integrated circuit device, semiconductor integrated c...

Semiconductor integrated circuit and power supply routing method an...

Automatic placement method for arranging logic cells

Automatic cell-layout arranging method and apparatus for polycell l...

Patents Applicationslast 30 patents

Noise suppression circuit, ASIC, navigation apparatus, communicatio...

Method of automatic layout design for LSI, mask set and semiconduct...

Noise suppression circuit, asic, navigation apparatus, communicatio...

Method for distributing clock signals to flip-flop circuits

Semiconductor integrated circuit device, semiconductor integrated c...

Semiconductor integrated circuit device, semiconductor integrated c...