Masashi Shimanouchi

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques for generating a PAM eye diagram in a receiver
- Patent number 12,003,352
- Issue date Jun 4, 2024
- Altera Corporation
- Peng Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Short link efficient interconnect circuitry
- Patent number 11,356,303
- Issue date Jun 7, 2022
- Intel Corporation
- Hsinho Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decomposable forward error correction
- Patent number 11,101,925
- Issue date Aug 24, 2021
- Intel Corporation
- Martin Langhammer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Short link efficient interconnect circuitry
- Patent number 10,965,501
- Issue date Mar 30, 2021
- Intel Corporation
- Hsinho Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Short link efficient interconnect circuitry
- Patent number 10,530,614
- Issue date Jan 7, 2020
- Intel Corporation
- Hsinho Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PAM-n jitter/noise decomposition analysis
- Patent number 10,476,716
- Issue date Nov 12, 2019
- Intel Corporation
- Mike Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for processing data and performing crosstalk s...
- Patent number 10,331,827
- Issue date Jun 25, 2019
- Altera Corporation
- Masashi Shimanouchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PAM-n jitter/noise decomposition analysis
- Patent number 10,020,967
- Issue date Jul 10, 2018
- Intel Corporation
- Mike Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Communication link control using communication interface and progra...
- Patent number 9,929,803
- Issue date Mar 27, 2018
- Altera Corporation
- Hsinho Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for built-in self-measurement of jitter for link components
- Patent number 9,596,160
- Issue date Mar 14, 2017
- Altera Corporation
- Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Simulation tool for high-speed communications links
- Patent number 9,405,865
- Issue date Aug 2, 2016
- Altera Corporation
- Peng Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for joint optimization of link equalization
- Patent number 9,237,044
- Issue date Jan 12, 2016
- Altera Corporation
- Hsinho Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-die jitter generator
- Patent number 9,222,972
- Issue date Dec 29, 2015
- Altera Corporation
- Weiqi Ding
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for generating short length patterns that ind...
- Patent number 9,177,087
- Issue date Nov 3, 2015
- Altera Corporation
- Masashi Shimanouchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for accurate transmitter simulation for link...
- Patent number 9,178,542
- Issue date Nov 3, 2015
- Altera Corporation
- Masashi Shimanouchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-level amplitude signaling receiver
- Patent number 8,750,406
- Issue date Jun 10, 2014
- Altera Corporation
- Mingde Pan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Simulation tool for high-speed communications links
- Patent number 8,626,474
- Issue date Jan 7, 2014
- Altera Corporation
- Peng Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry on an integrated circuit for performing or facilitating o...
- Patent number 8,504,882
- Issue date Aug 6, 2013
- Altera Corporation
- Peng Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit error rate checker receiving serial data signal from an eye viewer
- Patent number 8,433,958
- Issue date Apr 30, 2013
- Altera Corporation
- Weiqi Ding
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Programmable Multi-Protocol Adapter for Integrated Circuit
- Publication number 20250023959
- Publication date Jan 16, 2025
- Hsinho Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNIQUES FOR MONITORING AND CONTROL OF HIGH SPEED SERIAL COMMUNIC...
- Publication number 20230094919
- Publication date Mar 30, 2023
- Hsinho Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Systems and Methods for Supporting Both Pulse Amplitude Modulation...
- Publication number 20210328852
- Publication date Oct 21, 2021
- Masashi Shimanouchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Short Link Efficient Interconnect Circuitry
- Publication number 20210218603
- Publication date Jul 15, 2021
- Intel Corporation
- Hsinho Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques For Generating a PAM Eye Diagram in a Receiver
- Publication number 20210006439
- Publication date Jan 7, 2021
- Intel Corporation
- Peng Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Short Link Efficient Interconnect Circuitry
- Publication number 20200145260
- Publication date May 7, 2020
- Intel Corporation
- Hsinho Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOMPOSABLE FORWARD ERROR CORRECTION
- Publication number 20190190653
- Publication date Jun 20, 2019
- Intel Corporation
- Martin Langhammer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Short Link Efficient Interconnect Circuitry
- Publication number 20190132160
- Publication date May 2, 2019
- Intel Corporation
- Hsinho Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PAM-N JITTER/NOISE DECOMPOSITION ANALYSIS
- Publication number 20180316527
- Publication date Nov 1, 2018
- Intel Corporation
- Mike Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Simulation Tool for High-Speed Communications Links
- Publication number 20140107997
- Publication date Apr 17, 2014
- Altera Corporation
- Peng Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL AMPLITUDE SIGNALING RECEIVER
- Publication number 20130195155
- Publication date Aug 1, 2013
- Mingde PAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING O...
- Publication number 20120072784
- Publication date Mar 22, 2012
- Peng Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER
- Publication number 20120072785
- Publication date Mar 22, 2012
- Altera Corporation
- Weiqi Ding
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS
- Publication number 20110257953
- Publication date Oct 20, 2011
- Peng Li
- G06 - COMPUTING CALCULATING COUNTING

Masashi Shimanouchi

Person

Patents Grantslast 30 patents

Techniques for generating a PAM eye diagram in a receiver

Short link efficient interconnect circuitry

Decomposable forward error correction

Short link efficient interconnect circuitry

Short link efficient interconnect circuitry

PAM-n jitter/noise decomposition analysis

Method and apparatus for processing data and performing crosstalk s...

PAM-n jitter/noise decomposition analysis

Communication link control using communication interface and progra...

Methods for built-in self-measurement of jitter for link components

Simulation tool for high-speed communications links

Methods for joint optimization of link equalization

On-die jitter generator

Methods and apparatus for generating short length patterns that ind...

Methods and apparatus for accurate transmitter simulation for link...

Multi-level amplitude signaling receiver

Simulation tool for high-speed communications links

Circuitry on an integrated circuit for performing or facilitating o...

Bit error rate checker receiving serial data signal from an eye viewer

Patents Applicationslast 30 patents

Programmable Multi-Protocol Adapter for Integrated Circuit

TECHNIQUES FOR MONITORING AND CONTROL OF HIGH SPEED SERIAL COMMUNIC...

Systems and Methods for Supporting Both Pulse Amplitude Modulation...

Short Link Efficient Interconnect Circuitry

Techniques For Generating a PAM Eye Diagram in a Receiver

Short Link Efficient Interconnect Circuitry

DECOMPOSABLE FORWARD ERROR CORRECTION

Short Link Efficient Interconnect Circuitry

PAM-N JITTER/NOISE DECOMPOSITION ANALYSIS

Simulation Tool for High-Speed Communications Links

MULTI-LEVEL AMPLITUDE SIGNALING RECEIVER

CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING O...

BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER

SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS