Masataka Matsui

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and system
- Patent number 7,487,370
- Issue date Feb 3, 2009
- Kabushiki Kaisha Toshiba
- Shinichiro Shiratake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device composed of half cells
- Patent number 5,965,922
- Issue date Oct 12, 1999
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having bipolar transistor and MOS transistor
- Patent number 5,512,772
- Issue date Apr 30, 1996
- Kabushiki Kaisha Toshiba
- Takeo Maeda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit for generating input transition detection pulse
- Patent number 5,426,390
- Issue date Jun 20, 1995
- Kabushiki Kaisha Toshiba
- Tomoaki Yabe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device having bipolar transistor and MOS transistor
- Patent number 5,399,894
- Issue date Mar 21, 1995
- Kabushiki Kaisha Toshiba
- Takeo Maeda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Static random access memory capable of preventing erroneous writing
- Patent number 5,357,479
- Issue date Oct 18, 1994
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Read/write control device for random access memory
- Patent number 5,337,276
- Issue date Aug 9, 1994
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
BiCMOS logic circuit with bipolar transistor and MOS transistor for...
- Patent number 5,331,225
- Issue date Jul 19, 1994
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Static memory device
- Patent number 5,309,401
- Issue date May 3, 1994
- Kabushiki Kaisha Toshiba
- Azuma Suzuki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having identification region for carrying out...
- Patent number 5,294,812
- Issue date Mar 15, 1994
- Kabushiki Kaisha Toshiba
- Kazuhiko Hashimoto
- G01 - MEASURING TESTING
Information Patent Grant
Static semiconductor memory using thin film FET
- Patent number 5,278,459
- Issue date Jan 11, 1994
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory including stress test circuitry
- Patent number 5,276,647
- Issue date Jan 4, 1994
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
TTL to CMOS input buffer using CMOS structure
- Patent number 5,268,599
- Issue date Dec 7, 1993
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bi-CMOS semiconductor integrated circuit
- Patent number 5,243,557
- Issue date Sep 7, 1993
- Kabushiki Kaisha Toshiba
- Takeo Maeda
- G11 - INFORMATION STORAGE
Information Patent Grant
Static memory cell
- Patent number 5,239,501
- Issue date Aug 24, 1993
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Band-gap type voltage generating circuit for an ECL circuit
- Patent number 5,049,806
- Issue date Sep 17, 1991
- Kabushiki Kaisha Toshiba
- Yukihiro Urakawa
- G05 - CONTROLLING REGULATING
Information Patent Grant
Semiconductor logic circuit with a bipolar current mirror arrangement
- Patent number 5,027,009
- Issue date Jun 25, 1991
- Kabushiki Kaisha Toshiba
- Yukihiro Urakawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS static memory
- Patent number 5,010,521
- Issue date Apr 23, 1991
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Logic level converting circuit
- Patent number 4,992,681
- Issue date Feb 12, 1991
- Kabushiki Kaisha Toshiba
- Yukihiro Urakawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory device
- Patent number 4,987,560
- Issue date Jan 22, 1991
- Kabushiki Kaisha Toshiba
- Takahiro Hamano
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory
- Patent number 4,958,316
- Issue date Sep 18, 1990
- Kabushiki Kaisha Toshiba
- Kiyofumi Ochii
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory device with power down function
- Patent number 4,937,792
- Issue date Jun 26, 1990
- Kabushiki Kaisha Toshiba
- Azuma Suzuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device which can suppress operation error due...
- Patent number 4,931,998
- Issue date Jun 5, 1990
- Kabushiki Kaisha Toshiba
- Takayuki Ootani
- G11 - INFORMATION STORAGE
Information Patent Grant
Static semiconductor memory with section and block sense amplifiers
- Patent number 4,931,994
- Issue date Jun 5, 1990
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory with address transition detector
- Patent number 4,922,461
- Issue date May 1, 1990
- Kabushiki Kaisha Toshiba
- Shigeyuki Hayakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal synchronization type MOS SRAM with address transition dete...
- Patent number 4,916,668
- Issue date Apr 10, 1990
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory
- Patent number 4,901,284
- Issue date Feb 13, 1990
- Kabushiki Kaisha Toshiba
- Kiyofumi Ochii
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device using partial decoders for redundancy
- Patent number 4,881,202
- Issue date Nov 14, 1989
- Kabushiki Kaisha Toshiba
- Jun-ichi Tsujimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Static memory using a MIS field effect transistor
- Patent number 4,815,040
- Issue date Mar 21, 1989
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE
Information Patent Grant
Static memory with pull-up circuit for pulling-up a potential on a...
- Patent number 4,813,022
- Issue date Mar 14, 1989
- Kabushiki Kaisha Toshiba
- Masataka Matsui
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor device and system
- Publication number 20060271799
- Publication date Nov 30, 2006
- Kabushiki Kaisha Toshiba
- Shinichiro Shiratake
- G06 - COMPUTING CALCULATING COUNTING

Masataka Matsui

Person

Patents Grantslast 30 patents

Semiconductor device and system

Semiconductor memory device composed of half cells

Semiconductor device having bipolar transistor and MOS transistor

Circuit for generating input transition detection pulse

Semiconductor device having bipolar transistor and MOS transistor

Static random access memory capable of preventing erroneous writing

Read/write control device for random access memory

BiCMOS logic circuit with bipolar transistor and MOS transistor for...

Static memory device

Semiconductor device having identification region for carrying out...

Static semiconductor memory using thin film FET

Static random access memory including stress test circuitry

TTL to CMOS input buffer using CMOS structure

Bi-CMOS semiconductor integrated circuit

Static memory cell

Band-gap type voltage generating circuit for an ECL circuit

Semiconductor logic circuit with a bipolar current mirror arrangement

CMOS static memory

Logic level converting circuit

Semiconductor memory device

Static random access memory

Static random access memory device with power down function

Semiconductor memory device which can suppress operation error due...

Static semiconductor memory with section and block sense amplifiers

Static random access memory with address transition detector

Internal synchronization type MOS SRAM with address transition dete...

Static random access memory

Semiconductor memory device using partial decoders for redundancy

Static memory using a MIS field effect transistor

Static memory with pull-up circuit for pulling-up a potential on a...

Patents Applicationslast 30 patents

Semiconductor device and system