Mase Taub

Person

Elk Grove, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cross-point memory read technique to mitigate drift errors
- Patent number 12,230,346
- Issue date Feb 18, 2025
- Intel Corporation
- Hemant P. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Bipolar decoder for crosspoint memory
- Patent number 11,900,998
- Issue date Feb 13, 2024
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified write voltage for memory devices
- Patent number 11,705,197
- Issue date Jul 18, 2023
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Device, system and method to float a decoder for deselected address...
- Patent number 11,276,465
- Issue date Mar 15, 2022
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified write voltage for memory devices
- Patent number 11,170,853
- Issue date Nov 9, 2021
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual demarcation voltage sensing before writes
- Patent number 11,024,380
- Issue date Jun 1, 2021
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory control
- Patent number 10,546,634
- Issue date Jan 28, 2020
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point memory single-selection write technique
- Patent number 10,497,434
- Issue date Dec 3, 2019
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual demarcation voltage sensing before writes
- Patent number 10,482,960
- Issue date Nov 19, 2019
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,438,659
- Issue date Oct 8, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to mitigate bias drift for a memory device
- Patent number 10,269,396
- Issue date Apr 23, 2019
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory control
- Patent number 10,134,468
- Issue date Nov 20, 2018
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point memory single-selection write technique
- Patent number 10,056,136
- Issue date Aug 21, 2018
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,032,508
- Issue date Jul 24, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to mitigate bias drift for a memory device
- Patent number 10,026,460
- Issue date Jul 17, 2018
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory current
- Patent number 9,792,986
- Issue date Oct 17, 2017
- Intel Corporation
- Mase J. Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point memory single-selection write technique
- Patent number 9,685,204
- Issue date Jun 20, 2017
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Provision of holding current in non-volatile random access memory
- Patent number 9,685,213
- Issue date Jun 20, 2017
- Intel Corporation
- Dany-Sebastien Ly-Gagnon
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory control
- Patent number 9,601,193
- Issue date Mar 21, 2017
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to mitigate bias drift for a memory device
- Patent number 9,589,634
- Issue date Mar 7, 2017
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Grant
Provision of holding current in non-volatile random access memory
- Patent number 9,543,004
- Issue date Jan 10, 2017
- Intel Corporation
- Dany-Sebastien Ly-Gagnon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Cross-point memory single-selection write technique
- Patent number 9,384,831
- Issue date Jul 5, 2016
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point memory bias scheme
- Patent number 9,224,465
- Issue date Dec 29, 2015
- Intel Corporation
- Nathan R. Franklin
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus, system, and method for improving read endurance for a no...
- Patent number 8,954,650
- Issue date Feb 10, 2015
- Intel Corporation
- Hanmant P. Belgal
- G11 - INFORMATION STORAGE
Information Patent Grant
Cascode protected negative voltage switching
- Patent number 7,382,591
- Issue date Jun 3, 2008
- Intel Corporation
- Bi Han
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage tracking bias voltage
- Patent number 7,129,770
- Issue date Oct 31, 2006
- Intel Corporation
- Gerald J. Barkley
- G11 - INFORMATION STORAGE
Information Patent Grant
Providing protection against transistor junction breakdowns from su...
- Patent number 6,781,912
- Issue date Aug 24, 2004
- Intel Corporation
- Mase J. Taub
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus to provide a low voltage reference generation
- Patent number 6,628,108
- Issue date Sep 30, 2003
- Intel Corporation
- Mase Taub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing level shifter standby power consumption
- Patent number 6,532,178
- Issue date Mar 11, 2003
- Intel Corporation
- Mase J. Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Bi-voltage levels switches
- Patent number 6,522,180
- Issue date Feb 18, 2003
- Intel Corporation
- Raymond Zeng
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CROSS-POINT MEMORY READ TECHNIQUE TO MITIGATE DRIFT ERRORS
- Publication number 20220415425
- Publication date Dec 29, 2022
- Intel Corporation
- Hemant P. RAO
- G11 - INFORMATION STORAGE
Information Patent Application
BIPOLAR DECODER FOR CROSSPOINT MEMORY
- Publication number 20220084589
- Publication date Mar 17, 2022
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES
- Publication number 20220068385
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE, SYSTEM AND METHOD TO FLOAT A DECODER FOR DESELECTED ADDRESS...
- Publication number 20220059166
- Publication date Feb 24, 2022
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES
- Publication number 20210280244
- Publication date Sep 9, 2021
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES
- Publication number 20200160908
- Publication date May 21, 2020
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS POINT MEMORY CONTROL
- Publication number 20190096482
- Publication date Mar 28, 2019
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
- Publication number 20190074058
- Publication date Mar 7, 2019
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
- Publication number 20190057728
- Publication date Feb 21, 2019
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20190013071
- Publication date Jan 10, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20180190353
- Publication date Jul 5, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
- Publication number 20170294228
- Publication date Oct 12, 2017
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
- Publication number 20170287533
- Publication date Oct 5, 2017
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES
- Publication number 20170236580
- Publication date Aug 17, 2017
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS POINT MEMORY CONTROL
- Publication number 20170229172
- Publication date Aug 10, 2017
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS POINT MEMORY CONTROL
- Publication number 20170076794
- Publication date Mar 16, 2017
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Application
PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY
- Publication number 20170053698
- Publication date Feb 23, 2017
- Intel Corporation
- Dany-Sebastien Ly-Gagnon
- G11 - INFORMATION STORAGE
Information Patent Application
PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY
- Publication number 20160372194
- Publication date Dec 22, 2016
- Intel Corporation
- Dany-Sebastien Ly-Gagnon
- G11 - INFORMATION STORAGE
Information Patent Application
PHASE CHANGE MEMORY CURRENT
- Publication number 20160351258
- Publication date Dec 1, 2016
- Intel Corporation
- Mase J. Taub
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
- Publication number 20160336048
- Publication date Nov 17, 2016
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
- Publication number 20150348627
- Publication date Dec 3, 2015
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT MEMORY BIAS SCHEME
- Publication number 20150269994
- Publication date Sep 24, 2015
- Intel Corporation
- NATHAN R. FRANKLIN
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS, SYSTEM, AND METHOD FOR IMPROVING READ ENDURANCE FOR A NO...
- Publication number 20130073786
- Publication date Mar 21, 2013
- Hanmant P. Belgal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cascode protected negative voltage switching
- Publication number 20060267414
- Publication date Nov 30, 2006
- Bi Han
- G11 - INFORMATION STORAGE
Information Patent Application
High voltage tracking bias voltage
- Publication number 20060001479
- Publication date Jan 5, 2006
- Gerald J. Barkley
- G05 - CONTROLLING REGULATING
Information Patent Application
PROVIDING PROTECTION AGAINST TRANSISTOR JUNCTION BREAKDOWNS FROM SU...
- Publication number 20040124448
- Publication date Jul 1, 2004
- Mase J. Taub
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus to provide a low voltage reference generation
- Publication number 20030208699
- Publication date Nov 6, 2003
- Mase Taub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing level shifter standby power consumption
- Publication number 20020131306
- Publication date Sep 19, 2002
- Mase J. Taub
- G11 - INFORMATION STORAGE
Information Patent Application
VPX BANK ARCHITECTURE
- Publication number 20020018392
- Publication date Feb 14, 2002
- SANDEEP K. GULIANI
- G11 - INFORMATION STORAGE
Information Patent Application
VPX bank architecture
- Publication number 20010048627
- Publication date Dec 6, 2001
- Sandeep K. Guliani
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Cross-point memory read technique to mitigate drift errors

Bipolar decoder for crosspoint memory

Modified write voltage for memory devices

Device, system and method to float a decoder for deselected address...

Modified write voltage for memory devices

Dual demarcation voltage sensing before writes

Cross point memory control

Cross-point memory single-selection write technique

Dual demarcation voltage sensing before writes

Method and apparatus for multi-level setback read for three dimensi...

Techniques to mitigate bias drift for a memory device

Cross point memory control

Cross-point memory single-selection write technique

Method and apparatus for multi-level setback read for three dimensi...

Techniques to mitigate bias drift for a memory device

Phase change memory current

Cross-point memory single-selection write technique

Provision of holding current in non-volatile random access memory

Cross point memory control

Techniques to mitigate bias drift for a memory device

Provision of holding current in non-volatile random access memory

Cross-point memory single-selection write technique

Cross-point memory bias scheme

Apparatus, system, and method for improving read endurance for a no...

Cascode protected negative voltage switching

High voltage tracking bias voltage

Providing protection against transistor junction breakdowns from su...

Method and apparatus to provide a low voltage reference generation

Reducing level shifter standby power consumption

Bi-voltage levels switches

Patents Applicationslast 30 patents

CROSS-POINT MEMORY READ TECHNIQUE TO MITIGATE DRIFT ERRORS

BIPOLAR DECODER FOR CROSSPOINT MEMORY

MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES

DEVICE, SYSTEM AND METHOD TO FLOAT A DECODER FOR DESELECTED ADDRESS...

MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES

DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES

CROSS POINT MEMORY CONTROL

CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE

TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE

TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE

DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES

CROSS POINT MEMORY CONTROL

CROSS POINT MEMORY CONTROL

PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY

PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY

PHASE CHANGE MEMORY CURRENT

CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE

CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE

CROSS-POINT MEMORY BIAS SCHEME

APPARATUS, SYSTEM, AND METHOD FOR IMPROVING READ ENDURANCE FOR A NO...

Cascode protected negative voltage switching

High voltage tracking bias voltage

PROVIDING PROTECTION AGAINST TRANSISTOR JUNCTION BREAKDOWNS FROM SU...

Method and apparatus to provide a low voltage reference generation

Reducing level shifter standby power consumption

VPX BANK ARCHITECTURE

VPX bank architecture