Matthew A. Fisch

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,668,309
- Issue date Dec 23, 2003
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,578,116
- Issue date Jun 10, 2003
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,460,119
- Issue date Oct 1, 2002
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/n mode clocking scheme
- Patent number 6,268,749
- Issue date Jul 31, 2001
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch queue responsive to read request sequences
- Patent number 6,216,208
- Issue date Apr 10, 2001
- Intel Corporation
- Robert Greiner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read line buffer and signaling protocol for processor
- Patent number 6,209,068
- Issue date Mar 27, 2001
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/N mode clocking scheme
- Patent number 6,208,180
- Issue date Mar 27, 2001
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for generating bus clock signals with a 1/N characteristi...
- Patent number 6,114,887
- Issue date Sep 5, 2000
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction stall technique to prevent livelock in multiple-process...
- Patent number 6,078,981
- Issue date Jun 20, 2000
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus agent providing dynamic pipeline depth control
- Patent number 6,009,477
- Issue date Dec 28, 1999
- Intel Corporation
- Nitin Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for caching lock conditions in a multi-process...
- Patent number 6,006,299
- Issue date Dec 21, 1999
- Intel Corporation
- Wen-Hann Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus system providing dynamic control of pipeline depth for a multi-...
- Patent number 5,948,088
- Issue date Sep 7, 1999
- Intel Corporation
- Nitin Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting read, write, and invalidation o...
- Patent number 5,909,699
- Issue date Jun 1, 1999
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization mechanism for symmetric arbitration agents
- Patent number 5,901,297
- Issue date May 4, 1999
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system providing a universal architecture adaptive to a va...
- Patent number 5,896,513
- Issue date Apr 20, 1999
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signaling protocol conversion between a processor and a high-perfor...
- Patent number 5,845,107
- Issue date Dec 1, 1998
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/N mode clocking scheme
- Patent number 5,834,956
- Issue date Nov 10, 1998
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for preventing logic glitches in a 2/n clockin...
- Patent number 5,826,067
- Issue date Oct 20, 1998
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for generating bus clock signals with a 1/N characteristi...
- Patent number 5,802,132
- Issue date Sep 1, 1998
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for self-snooping a bus during a boundary tran...
- Patent number 5,797,026
- Issue date Aug 18, 1998
- Intel Corporation
- Michael W. Rhodehamel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically controlling bus access from a...
- Patent number 5,784,579
- Issue date Jul 21, 1998
- Intel Corporation
- Stephen S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing split lock variables in a comput...
- Patent number 5,778,441
- Issue date Jul 7, 1998
- Intel Corporation
- Michael W. Rhodehamel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining the timing of snoop windows in...
- Patent number 5,774,700
- Issue date Jun 30, 1998
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor subsystem for use with a universal computer architecture
- Patent number 5,764,934
- Issue date Jun 9, 1998
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus system providing dynamic control of pipeline depth for a multi-...
- Patent number 5,761,449
- Issue date Jun 2, 1998
- Intel Corporation
- Nitin Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system that maintains system wide cache coherency during d...
- Patent number 5,682,516
- Issue date Oct 28, 1997
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with distributed bus arbitration scheme for symmetr...
- Patent number 5,581,782
- Issue date Dec 3, 1996
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting read, write, and invalidation o...
- Patent number 5,572,702
- Issue date Nov 5, 1996
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for snoop stretching using signals that convey...
- Patent number 5,572,703
- Issue date Nov 5, 1996
- Intel Corporation
- Peter MacWilliams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method of handling race conditions in mesi-based mult...
- Patent number 5,551,005
- Issue date Aug 27, 1996
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Snoop blocking for cache coherency
- Publication number 20030115424
- Publication date Jun 19, 2003
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop blocking for cache coherency
- Publication number 20020199068
- Publication date Dec 26, 2002
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING

Matthew A. Fisch

Person

Patents Grantslast 30 patents

Snoop blocking for cache coherency

Snoop blocking for cache coherency

Snoop blocking for cache coherency

Core clock correction in a 2/n mode clocking scheme

Prefetch queue responsive to read request sequences

Read line buffer and signaling protocol for processor

Core clock correction in a 2/N mode clocking scheme

Apparatus for generating bus clock signals with a 1/N characteristi...

Transaction stall technique to prevent livelock in multiple-process...

Bus agent providing dynamic pipeline depth control

Apparatus and method for caching lock conditions in a multi-process...

Bus system providing dynamic control of pipeline depth for a multi-...

Method and apparatus for supporting read, write, and invalidation o...

Initialization mechanism for symmetric arbitration agents

Computer system providing a universal architecture adaptive to a va...

Signaling protocol conversion between a processor and a high-perfor...

Core clock correction in a 2/N mode clocking scheme

Method and apparatus for preventing logic glitches in a 2/n clockin...

Apparatus for generating bus clock signals with a 1/N characteristi...

Method and apparatus for self-snooping a bus during a boundary tran...

Method and apparatus for dynamically controlling bus access from a...

Method and apparatus for accessing split lock variables in a comput...

Method and apparatus for determining the timing of snoop windows in...

Processor subsystem for use with a universal computer architecture

Bus system providing dynamic control of pipeline depth for a multi-...

Computer system that maintains system wide cache coherency during d...

Computer system with distributed bus arbitration scheme for symmetr...

Method and apparatus for supporting read, write, and invalidation o...

Method and apparatus for snoop stretching using signals that convey...

Apparatus and method of handling race conditions in mesi-based mult...

Patents Applicationslast 30 patents

Snoop blocking for cache coherency

Snoop blocking for cache coherency