Matthew Ashcraft

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Implementation of load acquire/store release instructions using loa...
- Patent number 11,513,798
- Issue date Nov 29, 2022
- Ampere Computing LLC
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hazard prediction for a group of memory access instructions using a...
- Patent number 11,093,401
- Issue date Aug 17, 2021
- Ampere Computing LLC
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock control based on voltage associated with a microprocessor
- Patent number 10,348,281
- Issue date Jul 9, 2019
- Ampere Computing LLC
- David S. Oliver
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Allocation of load instruction(s) to a queue buffer in a processor...
- Patent number 9,880,849
- Issue date Jan 30, 2018
- MACOM CONNECTIVITY SOLUTIONS, LLC
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level store merging in a cache and memory hierarchy
- Patent number 9,280,479
- Issue date Mar 8, 2016
- Applied Micro Circuits Corporation
- David A. Kruckemyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Threshold controlled limited out of order load execution
- Patent number 8,949,581
- Issue date Feb 3, 2015
- Applied Micro Circuits Corporation
- Matthew W. Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Outstanding load miss buffer with shared entries
- Patent number 8,850,121
- Issue date Sep 30, 2014
- Applied Micro Circuits Corporation
- Matthew W. Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load store unit with load miss result buffer
- Patent number 8,806,135
- Issue date Aug 12, 2014
- Applied Micro Circuits Corporation
- Matthew W. Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load miss result buffer with shared data lines
- Patent number 8,793,435
- Issue date Jul 29, 2014
- Applied Micro Circuits Corporation
- Matthew W. Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symbolic renaming optimization of a trace
- Patent number 8,499,293
- Issue date Jul 30, 2013
- Oracle America, Inc.
- Matthew William Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trace unit
- Patent number 8,037,285
- Issue date Oct 11, 2011
- Oracle America, Inc.
- Richard Win Thaik
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for ensuring coherency in trace execution
- Patent number 8,032,710
- Issue date Oct 4, 2011
- Oracle America, Inc.
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for promoting traces in an instruction processing...
- Patent number 7,941,607
- Issue date May 10, 2011
- Oracle America, Inc.
- Richard Thaik
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Emit vector optimization of a trace
- Patent number 7,937,564
- Issue date May 3, 2011
- Oracle America, Inc.
- Matthew William Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prediction of data values read from memory by a microprocessor usin...
- Patent number 7,856,548
- Issue date Dec 21, 2010
- Oracle America, Inc.
- Chris Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flag optimization of a trace
- Patent number 7,849,292
- Issue date Dec 7, 2010
- Oracle America, Inc.
- Matthew William Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Promoting and appending traces in an instruction processing circuit...
- Patent number 7,814,298
- Issue date Oct 12, 2010
- Oracle America, Inc.
- Richard Thaik
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Prediction of data values read from memory by a microprocessor usin...
- Patent number 7,788,473
- Issue date Aug 31, 2010
- Oracle America, Inc.
- Chris Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graceful degradation in a trace-based processor
- Patent number 7,783,863
- Issue date Aug 24, 2010
- Oracle America, Inc.
- Christopher Patrick Nelson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A...
- Publication number 20150324203
- Publication date Nov 12, 2015
- Applied Micro Circuits Corporation
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTATION OF LOAD ACQUIRE/STORE RELEASE INSTRUCTIONS USING LOA...
- Publication number 20150317158
- Publication date Nov 5, 2015
- Applied Micro Circuits Corporation
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR...
- Publication number 20150160945
- Publication date Jun 11, 2015
- Applied Micro Circuits Corporation
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING

Matthew Ashcraft

Person

Patents Grantslast 30 patents

Implementation of load acquire/store release instructions using loa...

Hazard prediction for a group of memory access instructions using a...

Clock control based on voltage associated with a microprocessor

Allocation of load instruction(s) to a queue buffer in a processor...

Multi-level store merging in a cache and memory hierarchy

Threshold controlled limited out of order load execution

Outstanding load miss buffer with shared entries

Load store unit with load miss result buffer

Load miss result buffer with shared data lines

Symbolic renaming optimization of a trace

Trace unit

System and method for ensuring coherency in trace execution

Method and system for promoting traces in an instruction processing...

Emit vector optimization of a trace

Prediction of data values read from memory by a microprocessor usin...

Flag optimization of a trace

Promoting and appending traces in an instruction processing circuit...

Prediction of data values read from memory by a microprocessor usin...

Graceful degradation in a trace-based processor

Patents Applicationslast 30 patents

HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A...

IMPLEMENTATION OF LOAD ACQUIRE/STORE RELEASE INSTRUCTIONS USING LOA...

ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR...