Matthew D. Pierson

Person

Murphy, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Streaming engine with fetch ahead hysteresis
- Patent number 12,079,470
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with non-blocking high performance trans...
- Patent number 12,072,824
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 12,072,812
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor bridge with cache allocate awareness
- Patent number 11,907,528
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with wire reduction and physical congest...
- Patent number 11,803,505
- Issue date Oct 31, 2023
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slot/sub-slot prefetch architecture for multiple memory requestors
- Patent number 11,789,872
- Issue date Oct 17, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 11,755,203
- Issue date Sep 12, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for multi-endpoint heterogeneous coherent system
- Patent number 11,720,248
- Issue date Aug 8, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 11,687,238
- Issue date Jun 27, 2023
- Texas Instmments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure master and secure guest endpoint security firewall
- Patent number 11,501,024
- Issue date Nov 15, 2022
- Texas Instruments Incorporated
- Timothy D Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Credit aware central arbitration for multi-endpoint, multi-core system
- Patent number 11,429,526
- Issue date Aug 30, 2022
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 11,422,938
- Issue date Aug 23, 2022
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed error detection and correction with hamming code handoff
- Patent number 11,347,644
- Issue date May 31, 2022
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor, multi-domain, multi-protocol, cache coherent, spec...
- Patent number 11,341,052
- Issue date May 24, 2022
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with wire reduction and physical congest...
- Patent number 11,321,268
- Issue date May 3, 2022
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for multi-endpoint heterogeneous coherent system
- Patent number 11,307,988
- Issue date Apr 19, 2022
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 11,237,968
- Issue date Feb 1, 2022
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor bridge with cache allocate awareness
- Patent number 11,099,993
- Issue date Aug 24, 2021
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 11,099,994
- Issue date Aug 24, 2021
- Texas Instmments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 11,086,778
- Issue date Aug 10, 2021
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slot/sub-slot prefetch architecture for multiple memory requestors
- Patent number 11,074,190
- Issue date Jul 27, 2021
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with fetch ahead hysteresis
- Patent number 11,068,164
- Issue date Jul 20, 2021
- Texas Instruments Incorporated
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 11,036,648
- Issue date Jun 15, 2021
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-power-domain bridge with prefetch and write merging
- Patent number 10,990,529
- Issue date Apr 27, 2021
- Texas Instruments Incorporated
- Daniel Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 10,802,974
- Issue date Oct 13, 2020
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with non-blocking high performance trans...
- Patent number 10,795,844
- Issue date Oct 6, 2020
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with fetch ahead hysteresis
- Patent number 10,642,490
- Issue date May 5, 2020
- Texas Instruments Incorporated
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slot/sub-slot prefetch architecture for multiple memory requestors
- Patent number 10,394,718
- Issue date Aug 27, 2019
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with non-blocking high performance trans...
- Patent number 10,311,007
- Issue date Jun 4, 2019
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with fetch ahead hysteresis
- Patent number 10,209,887
- Issue date Feb 19, 2019
- Texas Instruments Incorporated
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
- Publication number 20240184446
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20230418469
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS
- Publication number 20230418759
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR COHERENT SYSTEM
- Publication number 20230384931
- Publication date Nov 30, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...
- Publication number 20230325078
- Publication date Oct 12, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL
- Publication number 20230048071
- Publication date Feb 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
- Publication number 20220374356
- Publication date Nov 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
- Publication number 20220374357
- Publication date Nov 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
- Publication number 20220283942
- Publication date Sep 8, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPEC...
- Publication number 20220269607
- Publication date Aug 25, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE BUS ARCHITECTURE WITH WIRE REDUCTION AND PHYSICAL CONGEST...
- Publication number 20220261373
- Publication date Aug 18, 2022
- TEXAS INSTRUMENTS INCORPORATED
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR MULTI-ENDPOINT HETEROGENEOUS COHERENT SYSTEM
- Publication number 20220229779
- Publication date Jul 21, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20220156192
- Publication date May 19, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...
- Publication number 20210382822
- Publication date Dec 9, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH FETCH AHEAD HYSTERESIS
- Publication number 20210349635
- Publication date Nov 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS
- Publication number 20210349827
- Publication date Nov 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
- Publication number 20210349821
- Publication date Nov 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20210326260
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE
- Publication number 20210240634
- Publication date Aug 5, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...
- Publication number 20210026768
- Publication date Jan 28, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE BUS ARCHITECTURE WITH NON-BLOCKING HIGH PERFORMANCE TRANS...
- Publication number 20210011872
- Publication date Jan 14, 2021
- TEXAS INSTRUMENTS INCORPORATED
- David M. THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH FETCH AHEAD HYSTERESIS
- Publication number 20200326854
- Publication date Oct 15, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20200117394
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPEC...
- Publication number 20200117621
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR MULTI-ENDPOINT HETEROGENEOUS COHERENT SYSTEM
- Publication number 20200117467
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
- Publication number 20200117619
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-POWER-DOMAIN BRIDGE WITH PREFETCH AND WRITE MERGING
- Publication number 20200117606
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Daniel WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
- Publication number 20200119753
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
- Publication number 20200117603
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
- Publication number 20200117395
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING

Matthew D. Pierson

Person

Patents Grantslast 30 patents

Streaming engine with fetch ahead hysteresis

Multicore bus architecture with non-blocking high performance trans...

Highly integrated scalable, flexible DSP megamodule architecture

Multi-processor bridge with cache allocate awareness

Multicore bus architecture with wire reduction and physical congest...

Slot/sub-slot prefetch architecture for multiple memory requestors

Multicore shared cache operation engine

Configurable cache for multi-endpoint heterogeneous coherent system

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Secure master and secure guest endpoint security firewall

Credit aware central arbitration for multi-endpoint, multi-core system

Multicore, multibank, fully concurrent coherence controller

Distributed error detection and correction with hamming code handoff

Multi-processor, multi-domain, multi-protocol, cache coherent, spec...

Multicore bus architecture with wire reduction and physical congest...

Configurable cache for multi-endpoint heterogeneous coherent system

Multicore shared cache operation engine

Multi-processor bridge with cache allocate awareness

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Multicore shared cache operation engine

Slot/sub-slot prefetch architecture for multiple memory requestors

Streaming engine with fetch ahead hysteresis

Highly integrated scalable, flexible DSP megamodule architecture

Multi-power-domain bridge with prefetch and write merging

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Multicore bus architecture with non-blocking high performance trans...

Streaming engine with fetch ahead hysteresis

Slot/sub-slot prefetch architecture for multiple memory requestors

Multicore bus architecture with non-blocking high performance trans...

Streaming engine with fetch ahead hysteresis

Patents Applicationslast 30 patents

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS

MULTICORE SHARED CACHE OPERATION ENGINE

SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS

CONFIGURABLE CACHE FOR COHERENT SYSTEM

VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...

SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL

CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF

MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPEC...

MULTICORE BUS ARCHITECTURE WITH WIRE REDUCTION AND PHYSICAL CONGEST...

CONFIGURABLE CACHE FOR MULTI-ENDPOINT HETEROGENEOUS COHERENT SYSTEM

MULTICORE SHARED CACHE OPERATION ENGINE

VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...

STREAMING ENGINE WITH FETCH AHEAD HYSTERESIS

SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS

MULTICORE SHARED CACHE OPERATION ENGINE

HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE

VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...

MULTICORE BUS ARCHITECTURE WITH NON-BLOCKING HIGH PERFORMANCE TRANS...

STREAMING ENGINE WITH FETCH AHEAD HYSTERESIS

MULTICORE SHARED CACHE OPERATION ENGINE

MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPEC...

CONFIGURABLE CACHE FOR MULTI-ENDPOINT HETEROGENEOUS COHERENT SYSTEM

CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM

MULTI-POWER-DOMAIN BRIDGE WITH PREFETCH AND WRITE MERGING

DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS