Matthew Herrick

Person

Mechanicville, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for fabricating a semiconductor integrated circuit with a li...
- Patent number 9,171,735
- Issue date Oct 27, 2015
- GLOBALFOUNDRIES, INC.
- Sohan Mehta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Reduced capacitance interlayer structures and fabrication methods
- Patent number 9,142,451
- Issue date Sep 22, 2015
- GLOBALFOUNDRIES Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a split gate memory cell
- Patent number 8,173,505
- Issue date May 8, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Matthew T. Herrick
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of forming a split gate non-volatile memory cell
- Patent number 7,838,363
- Issue date Nov 23, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Robert F. Steimle
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of forming a via
- Patent number 7,745,298
- Issue date Jun 29, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Tab A. Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a split gate memory device
- Patent number 7,416,945
- Issue date Aug 26, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Ramachandran Muralidhar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS
- Publication number 20150348907
- Publication date Dec 3, 2015
- GLOBAL FOUNDRIES Inc.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS
- Publication number 20150076705
- Publication date Mar 19, 2015
- GLOBALFOUNDRIES Inc.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH A LI...
- Publication number 20140235055
- Publication date Aug 21, 2014
- GLOBALFOUNDRIES, Inc.
- Sohan Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SPLIT GATE MEMORY CELL
- Publication number 20100099246
- Publication date Apr 22, 2010
- Matthew T. herrick
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD OF FORMING A VIA
- Publication number 20090142895
- Publication date Jun 4, 2009
- Tab A. Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SPLIT GATE NON-VOLATILE MEMORY CELL
- Publication number 20090111229
- Publication date Apr 30, 2009
- Robert F. Steimle
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE
- Publication number 20080199996
- Publication date Aug 21, 2008
- Ramachandran Muralidhar
- B82 - NANO-TECHNOLOGY

Matthew Herrick

Person

Patents Grantslast 30 patents

Method for fabricating a semiconductor integrated circuit with a li...

Reduced capacitance interlayer structures and fabrication methods

Method of making a split gate memory cell

Method of forming a split gate non-volatile memory cell

Method of forming a via

Method for forming a split gate memory device

Patents Applicationslast 30 patents

REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS

REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS

METHOD FOR FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH A LI...

METHOD OF MAKING A SPLIT GATE MEMORY CELL

METHOD OF FORMING A VIA

METHOD OF FORMING A SPLIT GATE NON-VOLATILE MEMORY CELL

METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE