Matthew W. Stoker

Person

Mesa, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Process of forming an electronic device including a layer of discon...
- Patent number 7,932,189
- Issue date Apr 26, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Tushar P. Merchant
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Transistor devices with nano-crystal gate structures
- Patent number 7,928,502
- Issue date Apr 19, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Chun-Li Liu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
MOS device with nano-crystal gate structure
- Patent number 7,700,438
- Issue date Apr 20, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS devices with multi-layer gate stack
- Patent number 7,683,443
- Issue date Mar 23, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS device with multi-layer gate stack
- Patent number 7,510,956
- Issue date Mar 31, 2009
- Fressscale Semiconductor, Inc.
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor fabrication process employing stress inducing source...
- Patent number 7,238,580
- Issue date Jul 3, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing SOI template layer
- Patent number 7,029,980
- Issue date Apr 18, 2006
- Freescale Semiconductor Inc.
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES
- Publication number 20100155825
- Publication date Jun 24, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Chun-Li Liu
- B82 - NANO-TECHNOLOGY
Information Patent Application
MOS DEVICES WITH MULTI-LAYER GATE STACK
- Publication number 20090115001
- Publication date May 7, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE INCLUDING A LAYER OF DISCONTINUOUS STORAGE ELEMEN...
- Publication number 20080182428
- Publication date Jul 31, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Tushar P. Merchant
- B82 - NANO-TECHNOLOGY
Information Patent Application
MOS device with nano-crystal gate structure
- Publication number 20070176227
- Publication date Aug 2, 2007
- Chun-Li Liu
- B82 - NANO-TECHNOLOGY
Information Patent Application
MOS device with multi-layer gate stack
- Publication number 20070176247
- Publication date Aug 2, 2007
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOSFET dielectric including a diffusion barrier
- Publication number 20070096226
- Publication date May 3, 2007
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming nanoclusters
- Publication number 20060189079
- Publication date Aug 24, 2006
- Tushar P. Merchant
- B82 - NANO-TECHNOLOGY
Information Patent Application
Semiconductor fabrication process employing stress inducing source...
- Publication number 20060166492
- Publication date Jul 27, 2006
- Freescale Semiconductor, Inc.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI template layer
- Publication number 20050070056
- Publication date Mar 31, 2005
- Chun-Li Liu
- H01 - BASIC ELECTRIC ELEMENTS

Matthew W. Stoker

Person

Patents Grantslast 30 patents

Process of forming an electronic device including a layer of discon...

Transistor devices with nano-crystal gate structures

MOS device with nano-crystal gate structure

MOS devices with multi-layer gate stack

MOS device with multi-layer gate stack

Semiconductor fabrication process employing stress inducing source...

Method of manufacturing SOI template layer

Patents Applicationslast 30 patents

TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES

MOS DEVICES WITH MULTI-LAYER GATE STACK

ELECTRONIC DEVICE INCLUDING A LAYER OF DISCONTINUOUS STORAGE ELEMEN...

MOS device with nano-crystal gate structure

MOS device with multi-layer gate stack

MOSFET dielectric including a diffusion barrier

Method of forming nanoclusters

Semiconductor fabrication process employing stress inducing source...

SOI template layer