Matthias Lehr

Person

Dresden, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Metal line layout based on line shifting
- Patent number 9,898,572
- Issue date Feb 20, 2018
- GLOBALFOUNDRIES Inc.
- Thomas Melde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits with metal-insulator-metal (MIM) capacitors and...
- Patent number 9,450,042
- Issue date Sep 20, 2016
- GLOBALFOUNDRIES, INC.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including a stress buffer material formed abov...
- Patent number 9,324,631
- Issue date Apr 26, 2016
- GLOBALFOUNDIRES INC.
- Axel Walter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with improved metal pillar configuration
- Patent number 9,136,234
- Issue date Sep 15, 2015
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device comprising a die seal having an integrated ali...
- Patent number 9,054,112
- Issue date Jun 9, 2015
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assessing thermal mechanical characteristics of complex semiconduct...
- Patent number 8,920,027
- Issue date Dec 30, 2014
- GLOBALFOUNDRIES Inc.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for forming a passivation layer without a terminal metal
- Patent number 8,841,140
- Issue date Sep 23, 2014
- Advanced Micro Devices, Inc.
- Tobias Letz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Protection of reactive metal surfaces of semiconductor devices duri...
- Patent number 8,828,888
- Issue date Sep 9, 2014
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for forming metal lines in a semiconductor by adapting th...
- Patent number 8,575,029
- Issue date Nov 5, 2013
- Advanced Micro Devices, Inc.
- Moritz Andreas Meyer
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method and device for fabricating bonding wires on the basis of mic...
- Patent number 8,561,446
- Issue date Oct 22, 2013
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- B21 - MECHANICAL METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL PUNCHING...
Information Patent Grant
Reduction of mechanical stress in metal stacks of sophisticated sem...
- Patent number 8,501,545
- Issue date Aug 6, 2013
- GLOBALFOUNDRIES Inc.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assessing metal stack integrity in sophisticated semiconductor devi...
- Patent number 8,479,578
- Issue date Jul 9, 2013
- GLOBALFOUNDRIES Inc.
- Holm Geisler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress reduction in chip packaging by using a low-temperature chip-...
- Patent number 8,482,123
- Issue date Jul 9, 2013
- GLOBALFOUNDRIES Inc.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a semiconductor device including a stress buffer...
- Patent number 8,450,206
- Issue date May 28, 2013
- GLOBALFOUNDRIES Inc.
- Axel Walter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a grain orientation layer
- Patent number 8,404,577
- Issue date Mar 26, 2013
- GLOBALFOUNDRIES Inc.
- Juergen Boemmels
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an alloy in an interconnect structure to increase...
- Patent number 8,329,577
- Issue date Dec 11, 2012
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including a die region designed for aluminum-f...
- Patent number 8,283,247
- Issue date Oct 9, 2012
- Advanced Micro Devices, Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonding on reactive metal surfaces of a metallization of a sem...
- Patent number 8,216,880
- Issue date Jul 10, 2012
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method and semiconductor structure for monitoring etch characterist...
- Patent number 8,114,688
- Issue date Feb 14, 2012
- Advanced Micro Devices, Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High yield plasma etch process for interlayer dielectrics
- Patent number 8,062,982
- Issue date Nov 22, 2011
- Advanced Micro Devices, Inc.
- Daniel Fischer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for forming metal lines in a semiconductor by adapting th...
- Patent number 8,058,731
- Issue date Nov 15, 2011
- Advanced Micro Devices, Inc.
- Moritz Andreas Meyer
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reduced wafer warpage in semiconductors by stress engineering in th...
- Patent number 8,053,354
- Issue date Nov 8, 2011
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonding on reactive metal surfaces of a metallization of a sem...
- Patent number 8,043,956
- Issue date Oct 25, 2011
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reducing contamination of semiconductor substrates during BEOL proc...
- Patent number 8,039,400
- Issue date Oct 18, 2011
- GLOBALFOUNDRIES Inc.
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including a reduced stress configuration for m...
- Patent number 8,039,958
- Issue date Oct 18, 2011
- Advanced Micro Devices, Inc.
- Alexander Platz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including stress relaxation gaps for enhancing...
- Patent number 7,982,313
- Issue date Jul 19, 2011
- Advanced Micro Devices, Inc.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch stop layer for a metallization layer with enhanced adhesion, e...
- Patent number 7,867,917
- Issue date Jan 11, 2011
- Advanced Micro Devices, Inc.
- Joerg Hohage
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Technique for forming contact insulation layers and silicide region...
- Patent number 7,838,359
- Issue date Nov 23, 2010
- Advanced Micro Devices, Inc.
- Christoph Schwan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and semiconductor structure for monitoring etch characterist...
- Patent number 7,829,889
- Issue date Nov 9, 2010
- Advanced Micro Devices, Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and test structure for monitoring CMP processes in metalliza...
- Patent number 7,829,357
- Issue date Nov 9, 2010
- GLOBALFOUNDRIES Inc.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METAL LINE LAYOUT BASED ON LINE SHIFTING
- Publication number 20170235867
- Publication date Aug 17, 2017
- GLOBALFOUNDRIES INC.
- Thomas Melde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE WITH IMPROVED METAL PILLAR CONFIGURATION
- Publication number 20150014843
- Publication date Jan 15, 2015
- GLOBALFOUNDRIES INC.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH METAL-INSULATOR-METAL (MIM) CAPACITORS AND...
- Publication number 20140035099
- Publication date Feb 6, 2014
- GLOBALFOUNDRIES INC.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOV...
- Publication number 20130234300
- Publication date Sep 12, 2013
- GLOBALFOUNDRIES INC.
- Axel Walter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal Features to Reduce Crack-Inducing Stresses in Metallization S...
- Publication number 20130087907
- Publication date Apr 11, 2013
- GLOBALFOUNDRIES INC.
- Matthias U. Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Die Seal for Integrated Circuit Device
- Publication number 20120286397
- Publication date Nov 15, 2012
- GLOBALFOUNDRIES INC.
- Frank Kuechenmeister
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTECTION OF REACTIVE METAL SURFACES OF SEMICONDUCTOR DEVICES DURI...
- Publication number 20120235285
- Publication date Sep 20, 2012
- GLOBALFOUNDRIES INC.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL HAVING AN INTEGRATED ALI...
- Publication number 20120223445
- Publication date Sep 6, 2012
- GLOBALFOUNDRIES INC.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING TH...
- Publication number 20120088365
- Publication date Apr 12, 2012
- Advanced Micro Devices, Inc.
- Moritz Andreas Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-...
- Publication number 20120049350
- Publication date Mar 1, 2012
- GLOBALFOUNDRIES INC.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Applying Thermal Mechanical Characteristics of Complex Semiconducto...
- Publication number 20120051392
- Publication date Mar 1, 2012
- GLOBALFOUNDRIES INC.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEM...
- Publication number 20120009780
- Publication date Jan 12, 2012
- GLOBALFOUNDRIES Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Comprising a Die Seal with Graded Pattern Density
- Publication number 20110291285
- Publication date Dec 1, 2011
- GLOBALFOUNDRIES INC.
- Guido Ueberreiter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reduction of Mechanical Stress in Metal Stacks of Sophisticated Sem...
- Publication number 20110244632
- Publication date Oct 6, 2011
- GLOBALFOUNDRIES INC.
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASSESSING METAL STACK INTEGRITY IN SOPHISTICATED SEMICONDUCTOR DEVI...
- Publication number 20110209548
- Publication date Sep 1, 2011
- Holm Geisler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Increasing Electromigration Resistance in an Interconnect Structure...
- Publication number 20110124189
- Publication date May 26, 2011
- GLOBALFOUNDRIES INC.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOV...
- Publication number 20110024900
- Publication date Feb 3, 2011
- Axel Walter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERIST...
- Publication number 20110020958
- Publication date Jan 27, 2011
- Advanced Micro Devices, Inc.
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STR...
- Publication number 20100252828
- Publication date Oct 7, 2010
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A COST-EFFICIENT CHIP-PACKAGE CONNEC...
- Publication number 20100164098
- Publication date Jul 1, 2010
- Frank Kuechenmeister
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND DEVICE FOR FABRICATING BONDING WIRES ON THE BASIS OF MIC...
- Publication number 20100107717
- Publication date May 6, 2010
- Matthias Lehr
- B21 - MECHANICAL METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL PUNCHING...
Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING A DISTRIBUTED INTERCONNECTED SENSOR...
- Publication number 20100109005
- Publication date May 6, 2010
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN TH...
- Publication number 20100109131
- Publication date May 6, 2010
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A REDUCED STRESS CONFIGURATION FOR M...
- Publication number 20100109158
- Publication date May 6, 2010
- Alexander Platz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING...
- Publication number 20100052147
- Publication date Mar 4, 2010
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICO...
- Publication number 20100052137
- Publication date Mar 4, 2010
- Andreas Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROC...
- Publication number 20090325378
- Publication date Dec 31, 2009
- Frank Koschinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORM...
- Publication number 20090294921
- Publication date Dec 3, 2009
- Michael Grillberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEM...
- Publication number 20090243105
- Publication date Oct 1, 2009
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INCREASING ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE...
- Publication number 20090197408
- Publication date Aug 6, 2009
- Matthias Lehr
- H01 - BASIC ELECTRIC ELEMENTS

Matthias Lehr

Person

Patents Grantslast 30 patents

Metal line layout based on line shifting

Integrated circuits with metal-insulator-metal (MIM) capacitors and...

Semiconductor device including a stress buffer material formed abov...

Semiconductor device with improved metal pillar configuration

Semiconductor device comprising a die seal having an integrated ali...

Assessing thermal mechanical characteristics of complex semiconduct...

Technique for forming a passivation layer without a terminal metal

Protection of reactive metal surfaces of semiconductor devices duri...

Technique for forming metal lines in a semiconductor by adapting th...

Method and device for fabricating bonding wires on the basis of mic...

Reduction of mechanical stress in metal stacks of sophisticated sem...

Assessing metal stack integrity in sophisticated semiconductor devi...

Stress reduction in chip packaging by using a low-temperature chip-...

Method of forming a semiconductor device including a stress buffer...

Semiconductor device having a grain orientation layer

Method of forming an alloy in an interconnect structure to increase...

Semiconductor device including a die region designed for aluminum-f...

Wire bonding on reactive metal surfaces of a metallization of a sem...

Method and semiconductor structure for monitoring etch characterist...

High yield plasma etch process for interlayer dielectrics

Technique for forming metal lines in a semiconductor by adapting th...

Reduced wafer warpage in semiconductors by stress engineering in th...

Wire bonding on reactive metal surfaces of a metallization of a sem...

Reducing contamination of semiconductor substrates during BEOL proc...

Semiconductor device including a reduced stress configuration for m...

Semiconductor device including stress relaxation gaps for enhancing...

Etch stop layer for a metallization layer with enhanced adhesion, e...

Technique for forming contact insulation layers and silicide region...

Method and semiconductor structure for monitoring etch characterist...

Method and test structure for monitoring CMP processes in metalliza...

Patents Applicationslast 30 patents

METAL LINE LAYOUT BASED ON LINE SHIFTING

SEMICONDUCTOR DEVICE WITH IMPROVED METAL PILLAR CONFIGURATION

INTEGRATED CIRCUITS WITH METAL-INSULATOR-METAL (MIM) CAPACITORS AND...

SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOV...

Metal Features to Reduce Crack-Inducing Stresses in Metallization S...

Die Seal for Integrated Circuit Device

PROTECTION OF REACTIVE METAL SURFACES OF SEMICONDUCTOR DEVICES DURI...

SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL HAVING AN INTEGRATED ALI...

TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING TH...

Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-...

Applying Thermal Mechanical Characteristics of Complex Semiconducto...

WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEM...

Semiconductor Device Comprising a Die Seal with Graded Pattern Density

Reduction of Mechanical Stress in Metal Stacks of Sophisticated Sem...

ASSESSING METAL STACK INTEGRITY IN SOPHISTICATED SEMICONDUCTOR DEVI...

Increasing Electromigration Resistance in an Interconnect Structure...

SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOV...

METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERIST...

SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STR...

SEMICONDUCTOR DEVICE INCLUDING A COST-EFFICIENT CHIP-PACKAGE CONNEC...

METHOD AND DEVICE FOR FABRICATING BONDING WIRES ON THE BASIS OF MIC...

SEMICONDUCTOR DEVICE COMPRISING A DISTRIBUTED INTERCONNECTED SENSOR...

REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN TH...

SEMICONDUCTOR DEVICE INCLUDING A REDUCED STRESS CONFIGURATION FOR M...

SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING...

ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICO...

REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROC...

SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORM...

WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEM...

INCREASING ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE...