Mayukh Bhattacharya

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Finding equivalent classes of hard defects in stacked MOSFET arrays
- Patent number 11,797,737
- Issue date Oct 24, 2023
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for custom model definition of analog defects in...
- Patent number 11,763,056
- Issue date Sep 19, 2023
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Visual representation to assess quality of input stimulus in transi...
- Patent number 11,734,482
- Issue date Aug 22, 2023
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic test pattern generation (ATPG) for parametric faults
- Patent number 11,669,667
- Issue date Jun 6, 2023
- Synopsys, Inc.
- Peilin Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistor—level defect coverage and defect simulation
- Patent number 11,620,424
- Issue date Apr 4, 2023
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast and scalable methodology for analog defect detectability analysis
- Patent number 11,579,994
- Issue date Feb 14, 2023
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Defect weight formulas for analog defect simulation
- Patent number 11,443,092
- Issue date Sep 13, 2022
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guiding sample size choice in analog defect or fault simulation
- Patent number 11,361,135
- Issue date Jun 14, 2022
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Visual representation of circuit related data
- Patent number 10,409,941
- Issue date Sep 10, 2019
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of optimizing capacitive couplings in high-capacitance nets...
- Patent number 9,032,352
- Issue date May 12, 2015
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic, hierarchy-independent partitioning method for transistor...
- Patent number 8,060,355
- Issue date Nov 15, 2011
- Synopsys, Inc.
- Kevin J. Kerns
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TEST POINT INSERTION IN ANALOG CIRCUIT DESIGN TESTING
- Publication number 20240232485
- Publication date Jul 11, 2024
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC TEST PATTERN GENERATION TO INCREASE COVERAGE IN DETECTING...
- Publication number 20240193336
- Publication date Jun 13, 2024
- Synopsys, Inc.
- Peilin Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEASURING DEVICE DEFECT SENSITIZATION IN TRANSISTOR-LEVEL CIRCUITS
- Publication number 20240061035
- Publication date Feb 22, 2024
- Synopsys, Inc.
- Mayukh BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR- LEVEL DEFECT COVERAGE AND DEFECT SIMULATION
- Publication number 20220121799
- Publication date Apr 21, 2022
- Synopsys, Inc.
- Mayukh BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GUIDING SAMPLE SIZE CHOICE IN ANALOG DEFECT OR FAULT SIMULATION
- Publication number 20210383047
- Publication date Dec 9, 2021
- Synopsys, Inc.
- Mayukh BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINDING EQUIVALENT CLASSES OF HARD DEFECTS IN STACKED MOSFET ARRAYS
- Publication number 20210374313
- Publication date Dec 2, 2021
- Synopsys, Inc.
- Mayukh BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFECT WEIGH FORMULAS FOR ANALOG DEFECT SIMULATION
- Publication number 20210350058
- Publication date Nov 11, 2021
- Synopsys, Inc.
- Mayukh BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR CUSTOM MODEL DEFINITION OF ANALOG DEFECTS IN...
- Publication number 20210326506
- Publication date Oct 21, 2021
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST AND SCALABLE METHODOLOGY FOR ANALOG DEFECT DETECTABILITY ANALYSIS
- Publication number 20210326227
- Publication date Oct 21, 2021
- Synopsys, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR FINDING EQUIVALENT CLASSES OF HARD DEFECTS IN STACKED MO...
- Publication number 20210312113
- Publication date Oct 7, 2021
- Synopsys, Inc.
- Mayukh BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC TEST PATTERN GENERATION (ATPG) FOR PARAMETRIC FAULTS
- Publication number 20210264087
- Publication date Aug 26, 2021
- Synopsys, Inc.
- Peilin Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Automated Optimized Personal Task Scheduling...
- Publication number 20160379175
- Publication date Dec 29, 2016
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VISUAL REPRESENTATION OF CIRCUIT RELATED DATA
- Publication number 20150120250
- Publication date Apr 30, 2015
- Synopsis, Inc.
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method Of Optimizing Capacitive Couplings In High-Capacitance Nets...
- Publication number 20140365986
- Publication date Dec 11, 2014
- Mayukh Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic, Hierarchy-Independent Partitioning Method For Transistor...
- Publication number 20090030665
- Publication date Jan 29, 2009
- Synopsys, Inc.
- Kevin J. Kerns
- G06 - COMPUTING CALCULATING COUNTING

Mayukh Bhattacharya

Person

Patents Grantslast 30 patents

Finding equivalent classes of hard defects in stacked MOSFET arrays

Method and system for custom model definition of analog defects in...

Visual representation to assess quality of input stimulus in transi...

Automatic test pattern generation (ATPG) for parametric faults

Transistor—level defect coverage and defect simulation

Fast and scalable methodology for analog defect detectability analysis

Defect weight formulas for analog defect simulation

Guiding sample size choice in analog defect or fault simulation

Visual representation of circuit related data

Method of optimizing capacitive couplings in high-capacitance nets...

Automatic, hierarchy-independent partitioning method for transistor...

Patents Applicationslast 30 patents

TEST POINT INSERTION IN ANALOG CIRCUIT DESIGN TESTING

AUTOMATIC TEST PATTERN GENERATION TO INCREASE COVERAGE IN DETECTING...

MEASURING DEVICE DEFECT SENSITIZATION IN TRANSISTOR-LEVEL CIRCUITS

TRANSISTOR- LEVEL DEFECT COVERAGE AND DEFECT SIMULATION

GUIDING SAMPLE SIZE CHOICE IN ANALOG DEFECT OR FAULT SIMULATION

FINDING EQUIVALENT CLASSES OF HARD DEFECTS IN STACKED MOSFET ARRAYS

DEFECT WEIGH FORMULAS FOR ANALOG DEFECT SIMULATION

METHOD AND SYSTEM FOR CUSTOM MODEL DEFINITION OF ANALOG DEFECTS IN...

FAST AND SCALABLE METHODOLOGY FOR ANALOG DEFECT DETECTABILITY ANALYSIS

METHOD FOR FINDING EQUIVALENT CLASSES OF HARD DEFECTS IN STACKED MO...

AUTOMATIC TEST PATTERN GENERATION (ATPG) FOR PARAMETRIC FAULTS

System and Method for Automated Optimized Personal Task Scheduling...

VISUAL REPRESENTATION OF CIRCUIT RELATED DATA

Method Of Optimizing Capacitive Couplings In High-Capacitance Nets...

Automatic, Hierarchy-Independent Partitioning Method For Transistor...