Mehmet Can Yildiz

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Maximum turn constraint for routing of integrated circuit designs
- Patent number 12,216,977
- Issue date Feb 4, 2025
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded network routing based on partitioning
- Patent number 11,928,500
- Issue date Mar 12, 2024
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing congestion based on fractional via cost and via density
- Patent number 11,734,485
- Issue date Aug 22, 2023
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing using rule-based blockage extension
- Patent number 11,675,955
- Issue date Jun 13, 2023
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing based on routing demand adjustment
- Patent number 11,461,530
- Issue date Oct 4, 2022
- Cadence Design Systems, Inc.
- Mateus Paiva Fogaça
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer assignment based on wirelength threshold
- Patent number 11,132,489
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer assignment and routing based on resistance or capacitance cha...
- Patent number 11,080,457
- Issue date Aug 3, 2021
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing based on pin placement within routing blockage
- Patent number 11,030,377
- Issue date Jun 8, 2021
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Track assignment by dynamic programming
- Patent number 11,030,378
- Issue date Jun 8, 2021
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing congestion based on layer-assigned net and placement blockage
- Patent number 10,997,352
- Issue date May 4, 2021
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying route topology to fix clock tree violations
- Patent number 10,963,617
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing congestion based on via spacing and pin density
- Patent number 10,885,257
- Issue date Jan 5, 2021
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for routing in an integrated circuit design
- Patent number 10,755,024
- Issue date Aug 25, 2020
- Cadence Design Systems, Inc.
- Wing Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing using multi-panel track assignment
- Patent number 10,706,201
- Issue date Jul 7, 2020
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing based on parallel run length rules
- Patent number 10,685,164
- Issue date Jun 16, 2020
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit routing based on enhanced topology
- Patent number 10,460,063
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing framework to resolve single-entry constraint violations for...
- Patent number 10,460,066
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partition-aware grid graph based hierarchical global routing
- Patent number 10,460,064
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing topology generation using spine-like tree structure
- Patent number 10,460,065
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for clustering pins for power
- Patent number 10,289,792
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing tree topology generation
- Patent number 10,289,795
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for constructing spanning trees
- Patent number 10,102,328
- Issue date Oct 16, 2018
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for congestion and routability aware detailed p...
- Patent number 10,031,994
- Issue date Jul 24, 2018
- Cadence Design Systems, Inc.
- Wen Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stability metrics for placement to quantify the stability of placem...
- Patent number 7,073,144
- Issue date Jul 4, 2006
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
System and Method of Eliminating Electrical Violations
- Publication number 20070283301
- Publication date Dec 6, 2007
- Arvind K. Karandikar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stability metrics for placement to quantify the stability of placem...
- Publication number 20050235237
- Publication date Oct 20, 2005
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING

Mehmet Can Yildiz

Person

Patents Grantslast 30 patents

Maximum turn constraint for routing of integrated circuit designs

Multi-threaded network routing based on partitioning

Routing congestion based on fractional via cost and via density

Routing using rule-based blockage extension

Circuit design routing based on routing demand adjustment

Layer assignment based on wirelength threshold

Layer assignment and routing based on resistance or capacitance cha...

Routing based on pin placement within routing blockage

Track assignment by dynamic programming

Routing congestion based on layer-assigned net and placement blockage

Modifying route topology to fix clock tree violations

Routing congestion based on via spacing and pin density

System and method for routing in an integrated circuit design

Circuit design routing using multi-panel track assignment

Circuit design routing based on parallel run length rules

Integrated circuit routing based on enhanced topology

Routing framework to resolve single-entry constraint violations for...

Partition-aware grid graph based hierarchical global routing

Routing topology generation using spine-like tree structure

Systems and methods for clustering pins for power

Routing tree topology generation

System and method for constructing spanning trees

Systems and methods for congestion and routability aware detailed p...

Stability metrics for placement to quantify the stability of placem...

Patents Applicationslast 30 patents

System and Method of Eliminating Electrical Violations

Stability metrics for placement to quantify the stability of placem...