Mehrdad Mahanpour

Person

Union City, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Contact liner in integrated circuit technology
- Patent number 7,670,915
- Issue date Mar 2, 2010
- Advanced Micro Devices, Inc.
- Errol Todd Ryan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for packaging test integrated circuits
- Patent number 7,093,209
- Issue date Aug 15, 2006
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for locating chip-level defects through emission...
- Patent number 6,995,564
- Issue date Feb 7, 2006
- Advanced Micro Devices, Inc.
- Boon Y. Ang
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for providing backside voltage contrast for silic...
- Patent number 6,991,946
- Issue date Jan 31, 2006
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for using emission microscopy in physical verific...
- Patent number 6,941,529
- Issue date Sep 6, 2005
- Advanced Micro Devices, Inc.
- Shivananda Shetty
- G01 - MEASURING TESTING
Information Patent Grant
Detecting heat generating failures in unpassivated semiconductor de...
- Patent number 6,866,416
- Issue date Mar 15, 2005
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for identifying individual die during failure...
- Patent number 6,830,941
- Issue date Dec 14, 2004
- Advanced Micro Devices, Inc.
- Chern-Jiann Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for revealing active regions in a SOI structure for DUT back...
- Patent number 6,770,495
- Issue date Aug 3, 2004
- Advanced Micro Devices, Inc.
- Boon Y. Ang
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for using TMAH for staining copper silicon on ins...
- Patent number 6,770,512
- Issue date Aug 3, 2004
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for reducing polymer build up during plasma etch...
- Patent number 6,528,332
- Issue date Mar 4, 2003
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for holding and delayering a semiconductor die
- Patent number 6,485,361
- Issue date Nov 26, 2002
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- B24 - GRINDING POLISHING
Information Patent Grant
How to improve the ESD on SOI devices
- Patent number 6,452,234
- Issue date Sep 17, 2002
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to decapsulate a FBGA package
- Patent number 6,395,129
- Issue date May 28, 2002
- Advanced Micro Devices, Inc.
- Joseph L. Vu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for plastic package decapsulation of electronic d...
- Patent number 6,387,206
- Issue date May 14, 2002
- Advanced Micro Devices, Inc.
- Ahmad Ghaemmaghami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for selectively disconnecting a redundant power d...
- Patent number 6,320,400
- Issue date Nov 20, 2001
- Advanced Micro Devices, Inc.
- J. Courtney Black
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for removing a die from a semiconductor package
- Patent number 6,309,899
- Issue date Oct 30, 2001
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Separation of a multi-layer integrated circuit device and package
- Patent number 6,304,792
- Issue date Oct 16, 2001
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for providing a library for identifying VCC to gr...
- Patent number 6,253,353
- Issue date Jun 26, 2001
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- G01 - MEASURING TESTING
Information Patent Grant
Support structure with multi-layer support material for use during...
- Patent number 6,227,941
- Issue date May 8, 2001
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for detecting faults in a flip-chip package
- Patent number 6,181,153
- Issue date Jan 30, 2001
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- G01 - MEASURING TESTING
Information Patent Grant
Package removal for FBGA devices
- Patent number 6,127,194
- Issue date Oct 3, 2000
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- G01 - MEASURING TESTING
Information Patent Grant
Support structure for use during package removal from a multi-layer...
- Patent number 6,076,686
- Issue date Jun 20, 2000
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for holding, grinding and polishing a packaged...
- Patent number 6,030,282
- Issue date Feb 29, 2000
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- B24 - GRINDING POLISHING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for packaging test integrated circuits
- Publication number 20050060673
- Publication date Mar 17, 2005
- Advanced Micro Devices, Inc.
- Mehrdad Mahanpour
- G01 - MEASURING TESTING
Information Patent Application
Siliciding spacer in integrated circuit technology
- Publication number 20050048731
- Publication date Mar 3, 2005
- Jeffrey P. Patton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and system for reducing polymer build up during plasma etch...
- Publication number 20020158247
- Publication date Oct 31, 2002
- Mehrdad Mahanpour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and system for decapsulating a multi-chip package
- Publication number 20020089066
- Publication date Jul 11, 2002
- Mohammad Massoodi
- H01 - BASIC ELECTRIC ELEMENTS

Mehrdad Mahanpour

Person

Patents Grantslast 30 patents

Contact liner in integrated circuit technology

Method and apparatus for packaging test integrated circuits

Method and system for locating chip-level defects through emission...

Method and system for providing backside voltage contrast for silic...

Method and system for using emission microscopy in physical verific...

Detecting heat generating failures in unpassivated semiconductor de...

Method and apparatus for identifying individual die during failure...

Method for revealing active regions in a SOI structure for DUT back...

Method and system for using TMAH for staining copper silicon on ins...

Method and system for reducing polymer build up during plasma etch...

Apparatus for holding and delayering a semiconductor die

How to improve the ESD on SOI devices

Process to decapsulate a FBGA package

Method and system for plastic package decapsulation of electronic d...

Method and system for selectively disconnecting a redundant power d...

Method and system for removing a die from a semiconductor package

Separation of a multi-layer integrated circuit device and package

Method and system for providing a library for identifying VCC to gr...

Support structure with multi-layer support material for use during...

Method and system for detecting faults in a flip-chip package

Package removal for FBGA devices

Support structure for use during package removal from a multi-layer...

Method and apparatus for holding, grinding and polishing a packaged...

Patents Applicationslast 30 patents

Method and apparatus for packaging test integrated circuits

Siliciding spacer in integrated circuit technology

Method and system for reducing polymer build up during plasma etch...

Method and system for decapsulating a multi-chip package