Mehrdad Mofidi

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Latched address multi-chunk write to EEPROM
- Patent number 7,890,694
- Issue date Feb 15, 2011
- SanDisk Corporation
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and method with bit line to bit line coupled co...
- Patent number 7,532,514
- Issue date May 12, 2009
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for controlling voltage in non-volatile memory systems
- Patent number 7,447,093
- Issue date Nov 4, 2008
- SanDisk Corporation
- Jun Li
- G11 - INFORMATION STORAGE
Information Patent Grant
System for controlling voltage in non-volatile memory systems
- Patent number 7,403,434
- Issue date Jul 22, 2008
- SanDisk Corporation
- Jun Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and method with bit line to bit line coupled co...
- Patent number 7,269,069
- Issue date Sep 11, 2007
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and method with bit line compensation dependent...
- Patent number 7,215,574
- Issue date May 8, 2007
- SanDisk Corporation
- Shahzad Khalid
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and method with bit line coupled compensation
- Patent number 7,064,980
- Issue date Jun 20, 2006
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and method with bit line compensation dependent...
- Patent number 6,956,770
- Issue date Oct 18, 2005
- SanDisk Corporation
- Shahzad Khalid
- G11 - INFORMATION STORAGE
Information Patent Grant
Latched address multi-chunk write to EEPROM
- Patent number 6,829,673
- Issue date Dec 7, 2004
- SanDisk Corporation
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Latched address multi-chunk write to EEPROM
- Patent number 6,542,956
- Issue date Apr 1, 2003
- SanDisk Corporation
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent write of multiple chunks of data into multiple subarrays...
- Patent number 6,157,983
- Issue date Dec 5, 2000
- SanDisk Corporation
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Plane decode/virtual sector architecture
- Patent number 6,069,039
- Issue date May 30, 2000
- SanDisk Corporation
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent write of multiple chunks of data into multiple subarrays...
- Patent number 5,890,192
- Issue date Mar 30, 1999
- SanDisk Corporation
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Plane decode/virtual sector architecture
- Patent number 5,798,968
- Issue date Aug 25, 1998
- SanDisk Corporation
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for manufacturing a programmable power generation circuit f...
- Patent number 5,693,570
- Issue date Dec 2, 1997
- SanDisk Corporation
- Raul-Ardian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable power generation circuit for flash EEPROM memory systems
- Patent number 5,621,685
- Issue date Apr 15, 1997
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EEPROM self-adaptive voltage generation circuit operative wit...
- Patent number 5,596,532
- Issue date Jan 21, 1997
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable power generation circuit for flash EEPROM memory systems
- Patent number 5,592,420
- Issue date Jan 7, 1997
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable power generation circuit for flash EEPROM memory systems
- Patent number 5,568,424
- Issue date Oct 22, 1996
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable power generation circuit for flash eeprom memory systems
- Patent number 5,563,825
- Issue date Oct 8, 1996
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable power generation circuit for flash EEPROM memory systems
- Patent number 5,508,971
- Issue date Apr 16, 1996
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS ring oscillator having frequency independent of supply voltage
- Patent number 4,910,471
- Issue date Mar 20, 1990
- ICT International CMOS Technology, Inc.
- Dhaval J. Brahmbhatt
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MANUAL SUSPEND AND RESUME FOR NON-VOLATILE MEMORY
- Publication number 20120167100
- Publication date Jun 28, 2012
- Yan Li
- G11 - INFORMATION STORAGE
Information Patent Application
Latched Address Multi-Chunk Write to EEPROM
- Publication number 20090228644
- Publication date Sep 10, 2009
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR CONTROLLING VOLTAGE IN NON-VOLATILE MEMORY SYSTEMS
- Publication number 20080159000
- Publication date Jul 3, 2008
- Jun Li
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM FOR CONTROLLING VOLTAGE IN NON-VOLATILE MEMORY SYSTEMS
- Publication number 20080158947
- Publication date Jul 3, 2008
- Jun Li
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Volatile Memory And Method With Bit Line To Bit Line Coupled Co...
- Publication number 20070297234
- Publication date Dec 27, 2007
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Volatile Memory and Method With Bit Line to Bit Line Coupled Co...
- Publication number 20060227614
- Publication date Oct 12, 2006
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile memory and method with bit line compensation dependent...
- Publication number 20060034121
- Publication date Feb 16, 2006
- Shahzad Khalid
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY AND METHOD WITH BIT LINE COUPLED COMPENSATION
- Publication number 20050057965
- Publication date Mar 17, 2005
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile memory and method with bit line compensation dependent...
- Publication number 20050057967
- Publication date Mar 17, 2005
- Shahzad Khalid
- G11 - INFORMATION STORAGE
Information Patent Application
Latched address multi-chunk write to EEPROM
- Publication number 20030200380
- Publication date Oct 23, 2003
- Douglas J. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Latched address multi-chunk write to EEPROM
- Publication number 20030061437
- Publication date Mar 27, 2003
- Douglas J. Lee
- G11 - INFORMATION STORAGE

Mehrdad Mofidi

Person

Patents Grantslast 30 patents

Latched address multi-chunk write to EEPROM

Non-volatile memory and method with bit line to bit line coupled co...

Method for controlling voltage in non-volatile memory systems

System for controlling voltage in non-volatile memory systems

Non-volatile memory and method with bit line to bit line coupled co...

Non-volatile memory and method with bit line compensation dependent...

Non-volatile memory and method with bit line coupled compensation

Non-volatile memory and method with bit line compensation dependent...

Latched address multi-chunk write to EEPROM

Latched address multi-chunk write to EEPROM

Concurrent write of multiple chunks of data into multiple subarrays...

Plane decode/virtual sector architecture

Concurrent write of multiple chunks of data into multiple subarrays...

Plane decode/virtual sector architecture

Process for manufacturing a programmable power generation circuit f...

Programmable power generation circuit for flash EEPROM memory systems

Flash EEPROM self-adaptive voltage generation circuit operative wit...

Programmable power generation circuit for flash EEPROM memory systems

Programmable power generation circuit for flash EEPROM memory systems

Programmable power generation circuit for flash eeprom memory systems

Programmable power generation circuit for flash EEPROM memory systems

CMOS ring oscillator having frequency independent of supply voltage

Patents Applicationslast 30 patents

MANUAL SUSPEND AND RESUME FOR NON-VOLATILE MEMORY

Latched Address Multi-Chunk Write to EEPROM

METHOD FOR CONTROLLING VOLTAGE IN NON-VOLATILE MEMORY SYSTEMS

SYSTEM FOR CONTROLLING VOLTAGE IN NON-VOLATILE MEMORY SYSTEMS

Non-Volatile Memory And Method With Bit Line To Bit Line Coupled Co...

Non-Volatile Memory and Method With Bit Line to Bit Line Coupled Co...

Non-volatile memory and method with bit line compensation dependent...

NON-VOLATILE MEMORY AND METHOD WITH BIT LINE COUPLED COMPENSATION

Non-volatile memory and method with bit line compensation dependent...

Latched address multi-chunk write to EEPROM

Latched address multi-chunk write to EEPROM