Meikei Ieong

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual trench isolation for CMOS with hybrid orientations
- Patent number 9,355,887
- Issue date May 31, 2016
- GLOBALFOUNDRIES Inc.
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structure and method for fabrication thereof using multiple cr...
- Patent number 8,158,481
- Issue date Apr 17, 2012
- International Business Machines Corporation
- Tze-Chiang Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual trench isolation for CMOS with hybrid orientations
- Patent number 8,097,516
- Issue date Jan 17, 2012
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact scheme for FINFET structures with multiple FINs
- Patent number 8,080,838
- Issue date Dec 20, 2011
- International Business Machines Corporation
- Leland Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned planar double-gate transistor structure
- Patent number 7,960,790
- Issue date Jun 14, 2011
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of electron and hole mobilities in <110> Si under biaxi...
- Patent number 7,943,486
- Issue date May 17, 2011
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of fabricating a hybrid substrate for high-per...
- Patent number 7,833,854
- Issue date Nov 16, 2010
- International Business Machines Corporation
- Meikei Ieong
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Hybrid orientation SOI substrates, and method for forming the same
- Patent number 7,834,425
- Issue date Nov 16, 2010
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of strained Ge into advanced CMOS technology
- Patent number 7,790,538
- Issue date Sep 7, 2010
- International Business Machines Corporation
- Huiling Shang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form Si-containing SOI and underlying substrate with diff...
- Patent number 7,759,772
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit and method of design
- Patent number 7,723,207
- Issue date May 25, 2010
- International Business Machines Corporation
- Syed M. Alam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-performance CMOS SOI devices on hybrid crystal-oriented substr...
- Patent number 7,713,807
- Issue date May 11, 2010
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried stress isolation for high-performance CMOS technology
- Patent number 7,704,839
- Issue date Apr 27, 2010
- International Business Machines Corporation
- MeiKei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for planar SOI substrate with multiple orientations
- Patent number 7,691,482
- Issue date Apr 6, 2010
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained silicon CMOS on hybrid crystal orientations
- Patent number 7,691,688
- Issue date Apr 6, 2010
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stressed field effect transistors on hybrid orientation substrate
- Patent number 7,687,829
- Issue date Mar 30, 2010
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal gated ultra short MOSFET devices
- Patent number 7,678,638
- Issue date Mar 16, 2010
- International Business Machines Corporation
- Jack Oon Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained complementary metal oxide semiconductor (CMOS) on rotated...
- Patent number 7,675,055
- Issue date Mar 9, 2010
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structure and method for fabrication thereof using multiple cr...
- Patent number 7,671,421
- Issue date Mar 2, 2010
- International Business Machines Corporation
- Tze-Chiang Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sectional field effect devices and method of fabrication
- Patent number 7,659,153
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double gated transistor and method of fabrication
- Patent number 7,645,650
- Issue date Jan 12, 2010
- International Business Machines Corporation
- Andres Bryant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Highly manufacturable SRAM cells in substrates with hybrid crystal...
- Patent number 7,605,447
- Issue date Oct 20, 2009
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-cost strained SOI substrate for high-performance CMOS technology
- Patent number 7,528,056
- Issue date May 5, 2009
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained MOS devices using source/drain epitaxy
- Patent number 7,525,161
- Issue date Apr 28, 2009
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for metal gated ultra short MOSFET devices
- Patent number 7,494,861
- Issue date Feb 24, 2009
- International Business Machines Corporation
- Jack Oon Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid substrate technology for high-mobility planar and multiple-g...
- Patent number 7,485,506
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate engineering for optimum CMOS device performance
- Patent number 7,482,216
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Victor W. C. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin Si channel MOSFET using a self-aligned oxygen implant an...
- Patent number 7,482,243
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Diane C. Boyd
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of electron and hole mobilities in <110> Si under biaxi...
- Patent number 7,462,525
- Issue date Dec 9, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra thin body fully-depleted SOI MOSFETs
- Patent number 7,459,752
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- Publication number 20120104511
- Publication date May 3, 2012
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CR...
- Publication number 20100112800
- Publication date May 6, 2010
- International Business Machines Corporation
- Tze-Chiang Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINs
- Publication number 20090212366
- Publication date Aug 27, 2009
- International Business Machines Corporation
- Leland Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal Gated Ultra Short MOSFET Devices
- Publication number 20080318374
- Publication date Dec 25, 2008
- International Business Machines Corporation
- Jack Oon Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- Publication number 20080290379
- Publication date Nov 27, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PER...
- Publication number 20080261354
- Publication date Oct 23, 2008
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sectional Field Effect Devices and Method of Fabrication
- Publication number 20080254577
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS
- Publication number 20080254594
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE
- Publication number 20080251817
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE
- Publication number 20080246090
- Publication date Oct 9, 2008
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integration of strained Ge into advanced CMOS technology
- Publication number 20080248616
- Publication date Oct 9, 2008
- International Business Machines Corporation
- Huiling Shang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...
- Publication number 20080206958
- Publication date Aug 28, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME
- Publication number 20080203442
- Publication date Aug 28, 2008
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Stress Isolation for High-Performance CMOS Technology
- Publication number 20080185658
- Publication date Aug 7, 2008
- International Business Machines Corporation
- MeiKei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained MOS devices using source/drain epitaxy
- Publication number 20080179627
- Publication date Jul 31, 2008
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-COST STRAINED SOI SUBSTRATE FOR HIGH-PERFORMANCE CMOS TECHNOLOGY
- Publication number 20080171423
- Publication date Jul 17, 2008
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT...
- Publication number 20080142852
- Publication date Jun 19, 2008
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM Si-CONTAINING SOI AND UNDERLYING SUBSTRATE WITH DIFF...
- Publication number 20080128866
- Publication date Jun 5, 2008
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal Gated Ultra Short MOSFET Devices
- Publication number 20080124860
- Publication date May 29, 2008
- International Business Machines Corporation
- Jack Oon Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTR...
- Publication number 20080096330
- Publication date Apr 24, 2008
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...
- Publication number 20080044987
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN
- Publication number 20080042140
- Publication date Feb 21, 2008
- International Business Machines Corperation
- Syed M. Alam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...
- Publication number 20080044966
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS
- Publication number 20080042202
- Publication date Feb 21, 2008
- International Business Machines Corporation
- MeiKei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED...
- Publication number 20080042215
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- Publication number 20080036028
- Publication date Feb 14, 2008
- International Business Machines Corporation
- Victor Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID SUBSTRATE TECHNOLOGY FOR HIGH-MOBILITY PLANAR AND MULTIPLE-G...
- Publication number 20080020521
- Publication date Jan 24, 2008
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN
- Publication number 20070287224
- Publication date Dec 13, 2007
- International Business Machines Corperation
- Syed M. Alam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Contact scheme for FINFET structures with multiple FINs
- Publication number 20070287256
- Publication date Dec 13, 2007
- International Business Machines Corporation
- Leland Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS structure and method for fabrication thereof using multiple cr...
- Publication number 20070278586
- Publication date Dec 6, 2007
- International Business Machines Corporation
- Tze-Chiang Chen
- H01 - BASIC ELECTRIC ELEMENTS

Meikei Ieong

Person

Patents Grantslast 30 patents

Dual trench isolation for CMOS with hybrid orientations

CMOS structure and method for fabrication thereof using multiple cr...

Dual trench isolation for CMOS with hybrid orientations

Contact scheme for FINFET structures with multiple FINs

Self-aligned planar double-gate transistor structure

Enhancement of electron and hole mobilities in <110> Si under biaxi...

Structure and method of fabricating a hybrid substrate for high-per...

Hybrid orientation SOI substrates, and method for forming the same

Integration of strained Ge into advanced CMOS technology

Method to form Si-containing SOI and underlying substrate with diff...

Three dimensional integrated circuit and method of design

High-performance CMOS SOI devices on hybrid crystal-oriented substr...

Buried stress isolation for high-performance CMOS technology

Structure for planar SOI substrate with multiple orientations

Strained silicon CMOS on hybrid crystal orientations

Stressed field effect transistors on hybrid orientation substrate

Metal gated ultra short MOSFET devices

Strained complementary metal oxide semiconductor (CMOS) on rotated...

CMOS structure and method for fabrication thereof using multiple cr...

Sectional field effect devices and method of fabrication

Double gated transistor and method of fabrication

Highly manufacturable SRAM cells in substrates with hybrid crystal...

Low-cost strained SOI substrate for high-performance CMOS technology

Strained MOS devices using source/drain epitaxy

Method for metal gated ultra short MOSFET devices

Hybrid substrate technology for high-mobility planar and multiple-g...

Substrate engineering for optimum CMOS device performance

Ultra-thin Si channel MOSFET using a self-aligned oxygen implant an...

Enhancement of electron and hole mobilities in <110> Si under biaxi...

Ultra thin body fully-depleted SOI MOSFETs

Patents Applicationslast 30 patents

DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS

CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CR...

CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINs

Metal Gated Ultra Short MOSFET Devices

DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS

STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PER...

Sectional Field Effect Devices and Method of Fabrication

STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS

STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE

SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE

Integration of strained Ge into advanced CMOS technology

ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...

HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME

Buried Stress Isolation for High-Performance CMOS Technology

Strained MOS devices using source/drain epitaxy

LOW-COST STRAINED SOI SUBSTRATE FOR HIGH-PERFORMANCE CMOS TECHNOLOGY

SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT...

METHOD TO FORM Si-CONTAINING SOI AND UNDERLYING SUBSTRATE WITH DIFF...

Metal Gated Ultra Short MOSFET Devices

HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTR...

ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...

THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN

ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXI...

QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS

STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED...

DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS

HYBRID SUBSTRATE TECHNOLOGY FOR HIGH-MOBILITY PLANAR AND MULTIPLE-G...

THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN

Contact scheme for FINFET structures with multiple FINs

CMOS structure and method for fabrication thereof using multiple cr...