Meng-Fang Hsu

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Routing structure of semiconductor device and forming method thereof
- Patent number 12,216,978
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Anurag Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for generating layout diagram including wiring ar...
- Patent number 12,216,981
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Fong-Yuan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating routing structure of semiconductor device
- Patent number 12,164,853
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Anurag Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device and method
- Patent number 11,943,939
- Issue date Mar 26, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Meng-Kai Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device
- Patent number 11,869,800
- Issue date Jan 9, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Harry-Hak-Lay Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of analyzing and detecting critical cells
- Patent number 11,829,700
- Issue date Nov 28, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Anurag Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for generating layout diagram including wiring arrangement
- Patent number 11,790,151
- Issue date Oct 17, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Fong-Yuan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating layout diagram including wiring arrangement
- Patent number 11,775,727
- Issue date Oct 3, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Fong-Yuan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of generating a layout diagram
- Patent number 11,741,286
- Issue date Aug 29, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of analyzing and detecting critical cells
- Patent number 11,288,436
- Issue date Mar 29, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Anurag Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of generating a layout diagram
- Patent number 11,062,076
- Issue date Jul 13, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of decomposing a layout for multiple-patterning lithography
- Patent number 10,977,420
- Issue date Apr 13, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor apparatus including uncrowned and crowned cells and m...
- Patent number 10,943,046
- Issue date Mar 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Prasenjit Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of revising a layout diagram
- Patent number 10,776,551
- Issue date Sep 15, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate structure and methods of forming metal gate isolation
- Patent number 10,770,559
- Issue date Sep 8, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chun-Sheng Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for legalizing mixed-cell height standard cells of IC
- Patent number 10,713,410
- Issue date Jul 14, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chao-Hung Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for fabricating a semiconductor device
- Patent number 10,692,750
- Issue date Jun 23, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Harry-Hak-Lay Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rule checking for multiple patterning technology
- Patent number 10,643,017
- Issue date May 5, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of decomposing a layout for multiple-patterning lithography
- Patent number 10,515,186
- Issue date Dec 24, 2019
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Kai Hsu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of reconfiguring uncrowned standard cells and semiconductor...
- Patent number 10,452,805
- Issue date Oct 22, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Prasenjit Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for legalizing mixed-cell height standard cells of IC
- Patent number 10,275,559
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chao-Hung Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of forming metal gate isolation
- Patent number 10,276,676
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chun-Sheng Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of decomposing a layout for multiple-patterning lithography
- Patent number 10,275,562
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of reconfiguring uncrowned standard cells and semiconductor...
- Patent number 10,169,520
- Issue date Jan 1, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Prasenjit Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for using multiple libraries with different cel...
- Patent number 10,162,929
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, device and computer program product for integrated circuit...
- Patent number 10,140,407
- Issue date Nov 27, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chia-Ming Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for triple-patterning friendly placement
- Patent number 10,089,433
- Issue date Oct 2, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout checking method for advanced double patterning photolithogra...
- Patent number 10,055,531
- Issue date Aug 21, 2018
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chung-Hsing Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor structure and manufacturing method thereof
- Patent number 10,043,712
- Issue date Aug 7, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Fang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device
- Patent number 9,972,524
- Issue date May 15, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Harry-Hak-Lay Chuang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ROUTING STRUCTURE OF SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF
- Publication number 20240378365
- Publication date Nov 14, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- ANURAG VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE
- Publication number 20230403868
- Publication date Dec 14, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jerry Chang Jui KAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING AR...
- Publication number 20230394219
- Publication date Dec 7, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING AR...
- Publication number 20230385522
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
- Publication number 20230377942
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Harry-Hak-Lay Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STANDARD CELL CHARACTERIZATION FOR INTERNAL CONDUCTIVE LINE OF CELL
- Publication number 20230259680
- Publication date Aug 17, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- SHI-HAN ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD AND SYSTEM OF ARRANGING PATTERNS OF...
- Publication number 20230259686
- Publication date Aug 17, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- ANURAG VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF IMPLEMENTING AN INTEGRATED CIRCUIT HAVING A NARROW-WIDTH...
- Publication number 20230237235
- Publication date Jul 27, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anurag VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR GENERATING ROUTING STRUCTURE OF SEMICONDUCTOR DEVICE
- Publication number 20230222278
- Publication date Jul 13, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- ANURAG VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT
- Publication number 20220382957
- Publication date Dec 1, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING STRUCTURE OF SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF
- Publication number 20220327277
- Publication date Oct 13, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- ANURAG VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE AND METHOD
- Publication number 20220216270
- Publication date Jul 7, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Kai HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ANALYZING AND DETECTING CRITICAL CELLS
- Publication number 20220198121
- Publication date Jun 23, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anurag VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF GENERATING A LAYOUT DIAGRAM
- Publication number 20210326510
- Publication date Oct 21, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Kai HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF ANALYZING AND DETECTING CRITICAL CELLS
- Publication number 20210240904
- Publication date Aug 5, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Anurag VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF GENERATING A LAYOUT DIAGRAM
- Publication number 20200380194
- Publication date Dec 3, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Kai HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Fabricating a Semiconductor Device
- Publication number 20200321238
- Publication date Oct 8, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Harry-Hak-Lay Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Decomposing a Layout for Multiple-Patterning Lithography
- Publication number 20200125787
- Publication date Apr 23, 2020
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR APPARATUS INCLUDING UNCROWNED AND CROWNED CELLS AND M...
- Publication number 20200050733
- Publication date Feb 13, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Prasenjit RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF REVISING A LAYOUT DIAGRAM
- Publication number 20200004912
- Publication date Jan 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Kai HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gate Structure and Methods of Forming Metal Gate Isolation
- Publication number 20190334003
- Publication date Oct 31, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Chun-Sheng Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT
- Publication number 20190286784
- Publication date Sep 19, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR LEGALIZING MIXED-CELL HEIGHT STANDARD CELLS OF IC
- Publication number 20190251224
- Publication date Aug 15, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chao-Hung WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Decomposing a Layout for Multiple-Patterning Lithography
- Publication number 20190251228
- Publication date Aug 15, 2019
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF RECONFIGURING UNCROWNED STANDARD CELLS AND SEMICONDUCTOR...
- Publication number 20190108305
- Publication date Apr 11, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Prasenjit RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Fabricating a Semiconductor Device
- Publication number 20180269099
- Publication date Sep 20, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Harry-Hak-Lay Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DESIGN RULE CHECKING FOR MULTIPLE PATTERNING TECHNOLOGY
- Publication number 20180239862
- Publication date Aug 23, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Meng-Kai HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Decomposing a Layout for Multiple-Patterning Lithography
- Publication number 20180150590
- Publication date May 31, 2018
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Kai Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR LEGALIZING MIXED-CELL HEIGHT STANDARD CELLS OF IC
- Publication number 20180144083
- Publication date May 24, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chao-Hung WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF RECONFIGURING UNCROWNED STANDARD CELLS AND SEMICONDUCTOR...
- Publication number 20180004886
- Publication date Jan 4, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Prasenjit RAY
- G06 - COMPUTING CALCULATING COUNTING

Meng-Fang Hsu

Person

Patents Grantslast 30 patents

Routing structure of semiconductor device and forming method thereof

System and method for generating layout diagram including wiring ar...

Method for generating routing structure of semiconductor device

Integrated circuit device and method

Method for fabricating a semiconductor device

Method of analyzing and detecting critical cells

System for generating layout diagram including wiring arrangement

Method for generating layout diagram including wiring arrangement

Method and system of generating a layout diagram

Method of analyzing and detecting critical cells

Method and system of generating a layout diagram

Method of decomposing a layout for multiple-patterning lithography

Semiconductor apparatus including uncrowned and crowned cells and m...

Method and system of revising a layout diagram

Gate structure and methods of forming metal gate isolation

Method for legalizing mixed-cell height standard cells of IC

Method for fabricating a semiconductor device

Rule checking for multiple patterning technology

Method of decomposing a layout for multiple-patterning lithography

Method of reconfiguring uncrowned standard cells and semiconductor...

Method for legalizing mixed-cell height standard cells of IC

Methods of forming metal gate isolation

Method of decomposing a layout for multiple-patterning lithography

Method of reconfiguring uncrowned standard cells and semiconductor...

Systems and methods for using multiple libraries with different cel...

Method, device and computer program product for integrated circuit...

Method for triple-patterning friendly placement

Layout checking method for advanced double patterning photolithogra...

Semiconductor structure and manufacturing method thereof

Method for fabricating a semiconductor device

Patents Applicationslast 30 patents

ROUTING STRUCTURE OF SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE

METHOD AND SYSTEM FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING AR...

SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING AR...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

STANDARD CELL CHARACTERIZATION FOR INTERNAL CONDUCTIVE LINE OF CELL

SEMICONDUCTOR DEVICE AND METHOD AND SYSTEM OF ARRANGING PATTERNS OF...

METHOD OF IMPLEMENTING AN INTEGRATED CIRCUIT HAVING A NARROW-WIDTH...

METHOD FOR GENERATING ROUTING STRUCTURE OF SEMICONDUCTOR DEVICE

SYSTEM FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT

ROUTING STRUCTURE OF SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

INTEGRATED CIRCUIT DEVICE AND METHOD

METHOD OF ANALYZING AND DETECTING CRITICAL CELLS

METHOD AND SYSTEM OF GENERATING A LAYOUT DIAGRAM

METHOD OF ANALYZING AND DETECTING CRITICAL CELLS

METHOD AND SYSTEM OF GENERATING A LAYOUT DIAGRAM

Method for Fabricating a Semiconductor Device

Method of Decomposing a Layout for Multiple-Patterning Lithography

SEMICONDUCTOR APPARATUS INCLUDING UNCROWNED AND CROWNED CELLS AND M...

METHOD AND SYSTEM OF REVISING A LAYOUT DIAGRAM

Gate Structure and Methods of Forming Metal Gate Isolation

METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT

METHOD FOR LEGALIZING MIXED-CELL HEIGHT STANDARD CELLS OF IC

Method of Decomposing a Layout for Multiple-Patterning Lithography

METHOD OF RECONFIGURING UNCROWNED STANDARD CELLS AND SEMICONDUCTOR...

Method for Fabricating a Semiconductor Device

DESIGN RULE CHECKING FOR MULTIPLE PATTERNING TECHNOLOGY

Method of Decomposing a Layout for Multiple-Patterning Lithography

METHOD FOR LEGALIZING MIXED-CELL HEIGHT STANDARD CELLS OF IC

METHOD OF RECONFIGURING UNCROWNED STANDARD CELLS AND SEMICONDUCTOR...