Menno Spijker

Person

Ottawa, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Hitless re-arrangements in coupled digital phase-locked loops
- Patent number 10,666,269
- Issue date May 26, 2020
- Integrated Device Technology, Inc.
- Menno Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time slotted bus system for multiple coupled digital phase-locked l...
- Patent number 10,637,482
- Issue date Apr 28, 2020
- Integrated Device Technology, Inc.
- Menno Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time slotted bus system for multiple coupled digital phase-locked l...
- Patent number 10,476,509
- Issue date Nov 12, 2019
- Integrated Device Technology, Inc.
- Menno Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hitless re-arrangements in coupled digital phase-locked loops
- Patent number 10,355,699
- Issue date Jul 16, 2019
- Integrated Device Technology, Inc.
- Menno Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for transmitting data over a clock signal
- Patent number 9,628,255
- Issue date Apr 18, 2017
- Integrated Device Technology, Inc.
- Zaher Baidas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for synchronizing operations using separate a...
- Patent number 9,479,182
- Issue date Oct 25, 2016
- Integrated Device Technology, Inc.
- Zaher Baidas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-coupled phase-locked loops for clock and packet-based synchron...
- Patent number 9,369,270
- Issue date Jun 14, 2016
- Integrated Device Technology, Inc.
- Menno Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase locked loop fast lock method
- Patent number 7,369,002
- Issue date May 6, 2008
- Zarlink Semiconductor, Inc.
- Menno Tjeerd Spijker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Digital phase-locked loop with master-slave modes
- Patent number 7,242,740
- Issue date Jul 10, 2007
- Zarlink Semiconductor Inc.
- Menno Tjeerd Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock recovery PLL
- Patent number 6,959,064
- Issue date Oct 25, 2005
- Zarlink Semiconductor Inc.
- Menno Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
TIME SLOTTED BUS SYSTEM FOR MULTIPLE COUPLED DIGITAL PHASE-LOCKED L...
- Publication number 20200021296
- Publication date Jan 16, 2020
- Integrated Device Technology, Inc.
- Menno Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS
- Publication number 20190312580
- Publication date Oct 10, 2019
- Integrated Device Technology, Inc.
- Menno Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS
- Publication number 20180159542
- Publication date Jun 7, 2018
- Integrated Device Technology, Inc.
- Menno Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIME SLOTTED BUS SYSTEM FOR MULTIPLE COUPLED DIGITAL PHASE-LOCKED L...
- Publication number 20180159541
- Publication date Jun 7, 2018
- Integrated Device Technology, Inc.
- Menno Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase Locked Loop Fast Lock Method
- Publication number 20070024383
- Publication date Feb 1, 2007
- Zarlink Semiconductor Inc.
- Menno Tjeerd Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Phase-Locked Loop with Master-Slave Modes
- Publication number 20040208256
- Publication date Oct 21, 2004
- Menno Tjeerd Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock recovery PLL
- Publication number 20020044620
- Publication date Apr 18, 2002
- Menno Spijker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Menno Spijker

Person

Patents Grantslast 30 patents

Hitless re-arrangements in coupled digital phase-locked loops

Time slotted bus system for multiple coupled digital phase-locked l...

Time slotted bus system for multiple coupled digital phase-locked l...

Hitless re-arrangements in coupled digital phase-locked loops

Methods and apparatus for transmitting data over a clock signal

Methods and apparatus for synchronizing operations using separate a...

Dual-coupled phase-locked loops for clock and packet-based synchron...

Phase locked loop fast lock method

Digital phase-locked loop with master-slave modes

Clock recovery PLL

Patents Applicationslast 30 patents

TIME SLOTTED BUS SYSTEM FOR MULTIPLE COUPLED DIGITAL PHASE-LOCKED L...

HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS

HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS

TIME SLOTTED BUS SYSTEM FOR MULTIPLE COUPLED DIGITAL PHASE-LOCKED L...

Phase Locked Loop Fast Lock Method

Digital Phase-Locked Loop with Master-Slave Modes

Clock recovery PLL