Michael A. Kazda

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Netlist design for post silicon local clock controller timing impro...
- Patent number 12,282,721
- Issue date Apr 22, 2025
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated design closure with abutted hierarchy
- Patent number 11,080,456
- Issue date Aug 3, 2021
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of vectorized latches in hierarchical integrated circuit...
- Patent number 10,831,965
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local clock buffer controller placement and connectivity
- Patent number 10,831,967
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Jesse Surprise
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic microprocessor gate design tool for area/timing margin control
- Patent number 10,671,791
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Engineering change order aware global routing
- Patent number 10,606,976
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Michael A Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic microprocessor gate design tool for area/timing margin control
- Patent number 10,078,722
- Issue date Sep 18, 2018
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of improving timing critical cells for physical design in th...
- Patent number 9,075,948
- Issue date Jul 7, 2015
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing refinement re-routing
- Patent number 8,635,577
- Issue date Jan 21, 2014
- International Business Machines Corporation
- Michael Anthony Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for sign-off timing closure of a VLSI chip
- Patent number 7,581,201
- Issue date Aug 25, 2009
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PREDICTING LOCAL LAYOUT EFFECTS USING A VARIATIONAL AUTOENCODER WIT...
- Publication number 20250077888
- Publication date Mar 6, 2025
- International Business Machines Corporation
- MICHAEL DANIEL MONKOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTING OPTIMAL PARAMETERS FOR PHYSICAL DESIGN SYNTHESIS
- Publication number 20240362459
- Publication date Oct 31, 2024
- International Business Machines Corporation
- Michael KAZDA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETLIST DESIGN FOR POST SILICON LOCAL CLOCK CONTROLLER TIMING IMPRO...
- Publication number 20230281365
- Publication date Sep 7, 2023
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY
- Publication number 20210165856
- Publication date Jun 3, 2021
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL
- Publication number 20180330039
- Publication date Nov 15, 2018
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENGINEERING CHANGE ORDER AWARE GLOBAL ROUTING
- Publication number 20180285507
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL
- Publication number 20170357747
- Publication date Dec 14, 2017
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Improving Timing Critical Cells For Physical Design In Th...
- Publication number 20150040095
- Publication date Feb 5, 2015
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING REFINEMENT RE-ROUTING
- Publication number 20130326458
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Michael Anthony Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-ROUTING COUPLING FIXES FOR INTEGRATED CIRCUITS
- Publication number 20100257503
- Publication date Oct 7, 2010
- International Business Machines Corporation
- Markus Buehler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP
- Publication number 20080209376
- Publication date Aug 28, 2008
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING

Michael A. Kazda

Person

Patents Grantslast 30 patents

Netlist design for post silicon local clock controller timing impro...

Automated design closure with abutted hierarchy

Placement of vectorized latches in hierarchical integrated circuit...

Local clock buffer controller placement and connectivity

Dynamic microprocessor gate design tool for area/timing margin control

Engineering change order aware global routing

Dynamic microprocessor gate design tool for area/timing margin control

Method of improving timing critical cells for physical design in th...

Timing refinement re-routing

System and method for sign-off timing closure of a VLSI chip

Patents Applicationslast 30 patents

PREDICTING LOCAL LAYOUT EFFECTS USING A VARIATIONAL AUTOENCODER WIT...

PREDICTING OPTIMAL PARAMETERS FOR PHYSICAL DESIGN SYNTHESIS

NETLIST DESIGN FOR POST SILICON LOCAL CLOCK CONTROLLER TIMING IMPRO...

AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY

DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL

ENGINEERING CHANGE ORDER AWARE GLOBAL ROUTING

DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL

Method of Improving Timing Critical Cells For Physical Design In Th...

TIMING REFINEMENT RE-ROUTING

POST-ROUTING COUPLING FIXES FOR INTEGRATED CIRCUITS

SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP