Michael B. Spear

Person

Round Rock, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Calibrating a quadrature receive serial interface
- Patent number 11,973,630
- Issue date Apr 30, 2024
- International Business Machines Corporation
- Michael B. Spear
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-latency deserializer having fine granularity and defective-lane...
- Patent number 11,907,074
- Issue date Feb 20, 2024
- International Business Machines Corporation
- Patrick James Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency of memory read operations returning data on a read...
- Patent number 11,099,601
- Issue date Aug 24, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Staged power on/off sequence at the I/O phy level in an interchip i...
- Patent number 10,901,936
- Issue date Jan 26, 2021
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing chip latency at a clock boundary by reference clock phase...
- Patent number 10,771,068
- Issue date Sep 8, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency of memory read operations returning data on a read...
- Patent number 10,698,440
- Issue date Jun 30, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test for receiver channel
- Patent number 10,608,763
- Issue date Mar 31, 2020
- International Business Machines Corporation
- John G. Rell
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Double data rate (DDR) memory read latency reduction
- Patent number 10,162,773
- Issue date Dec 25, 2018
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power reduction in a parallel data communications interface using c...
- Patent number 9,715,270
- Issue date Jul 25, 2017
- International Business Machines Corporation
- Steven J. Baumgartner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power reduction in a parallel data communications interface using c...
- Patent number 9,474,034
- Issue date Oct 18, 2016
- International Business Machines Corporation
- Steven J. Baumgartner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method to inject a bit error on a bus lane
- Patent number 9,092,312
- Issue date Jul 28, 2015
- International Business Machines Corporation
- Patrick J. Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel data communications mechanism having reduced power continu...
- Patent number 8,898,504
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Steven J. Baumgartner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic fault detection and repair in a data communications mechanism
- Patent number 8,767,531
- Issue date Jul 1, 2014
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Calibration of multiple parallel data communications lines for high...
- Patent number 8,681,839
- Issue date Mar 25, 2014
- International Business Machines Corporation
- John F. Bulzacchelli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power-on initialization and test for a cascade interconnect memory...
- Patent number 8,139,430
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Peter L. Buchmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Combined alignment scrambler function for elastic interface
- Patent number 8,001,412
- Issue date Aug 16, 2011
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Combined alignment scrambler function for elastic interface
- Patent number 7,412,618
- Issue date Aug 12, 2008
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
LOW-LATENCY DESERIALIZER HAVING FINE GRANULARITY AND DEFECTIVE-LANE...
- Publication number 20230115533
- Publication date Apr 13, 2023
- International Business Machines Corporation
- Patrick James Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...
- Publication number 20190384352
- Publication date Dec 19, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST FOR RECEIVER CHANNEL
- Publication number 20190363813
- Publication date Nov 28, 2019
- International Business Machines Corporation
- John G. RELL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
REDUCING CHIP LATENCY AT A CLOCK BOUNDARY BY REFERENCE CLOCK PHASE...
- Publication number 20190260380
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...
- Publication number 20190212769
- Publication date Jul 11, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STAGED POWER ON/OFF SEQUENCE AT THE I/O PHY LEVEL IN AN INTERCHIP I...
- Publication number 20180024963
- Publication date Jan 25, 2018
- International Business Machines Corporation
- DANIEL M. DREPS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Reduction in a Parallel Data Communications Interface Using C...
- Publication number 20170153689
- Publication date Jun 1, 2017
- International Business Machines Corporation
- Steven J. Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO INJECT A BIT ERROR ON A BUS LANE
- Publication number 20140173361
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Patrick J. Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communicating Control Information for a Data Communications Link Vi...
- Publication number 20130188656
- Publication date Jul 25, 2013
- International Business Machines Corporation
- Frank D. Ferraiolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel Data Communications Mechanism Having Reduced Power Continu...
- Publication number 20130159761
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Steven J. Baumgartner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dynamic Fault Detection and Repair in a Data Communications Mechanism
- Publication number 20120151247
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Coordinating Communications Interface Activities in Data Communicat...
- Publication number 20120106539
- Publication date May 3, 2012
- International Business Machines Corporation
- Frank D. Ferraiolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calibration of Multiple Parallel Data Communications Lines for High...
- Publication number 20120106687
- Publication date May 3, 2012
- International Business Machines Corporation
- John F. Bulzacchelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY...
- Publication number 20100005281
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Peter L. Buchmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Arrangements for Operating In-Line Memory Module Configurations
- Publication number 20090276559
- Publication date Nov 5, 2009
- International Business Machines Corporation
- James J. Allen, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINED ALIGNMENT SCRAMBLER FUNCTION FOR ELASTIC INTERFACE
- Publication number 20080201599
- Publication date Aug 21, 2008
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Combined alignment scrambler function for elastic interface
- Publication number 20060193395
- Publication date Aug 31, 2006
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Michael B. Spear

Person

Patents Grantslast 30 patents

Calibrating a quadrature receive serial interface

Low-latency deserializer having fine granularity and defective-lane...

Reducing latency of memory read operations returning data on a read...

Staged power on/off sequence at the I/O phy level in an interchip i...

Reducing chip latency at a clock boundary by reference clock phase...

Reducing latency of memory read operations returning data on a read...

Built-in self-test for receiver channel

Double data rate (DDR) memory read latency reduction

Power reduction in a parallel data communications interface using c...

Power reduction in a parallel data communications interface using c...

System and method to inject a bit error on a bus lane

Parallel data communications mechanism having reduced power continu...

Dynamic fault detection and repair in a data communications mechanism

Calibration of multiple parallel data communications lines for high...

Power-on initialization and test for a cascade interconnect memory...

Combined alignment scrambler function for elastic interface

Combined alignment scrambler function for elastic interface

Patents Applicationslast 30 patents

LOW-LATENCY DESERIALIZER HAVING FINE GRANULARITY AND DEFECTIVE-LANE...

REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...

BUILT-IN SELF-TEST FOR RECEIVER CHANNEL

REDUCING CHIP LATENCY AT A CLOCK BOUNDARY BY REFERENCE CLOCK PHASE...

REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...

STAGED POWER ON/OFF SEQUENCE AT THE I/O PHY LEVEL IN AN INTERCHIP I...

Power Reduction in a Parallel Data Communications Interface Using C...

SYSTEM AND METHOD TO INJECT A BIT ERROR ON A BUS LANE

Communicating Control Information for a Data Communications Link Vi...

Parallel Data Communications Mechanism Having Reduced Power Continu...

Dynamic Fault Detection and Repair in a Data Communications Mechanism

Coordinating Communications Interface Activities in Data Communicat...

Calibration of Multiple Parallel Data Communications Lines for High...

POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY...

Arrangements for Operating In-Line Memory Module Configurations

COMBINED ALIGNMENT SCRAMBLER FUNCTION FOR ELASTIC INTERFACE

Combined alignment scrambler function for elastic interface