Michael Bozich Calhoun

Person

Roseville, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic processor cache to avoid speculative vulnerability
- Patent number 11,169,805
- Issue date Nov 9, 2021
- Hewlett Packard Enterprise Development LP
- Michael Bozich Calhoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mesh configuration network
- Patent number 11,109,427
- Issue date Aug 31, 2021
- Hewlett Packard Enterprise Development LP
- Mark Gordon Fraser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System wide manageability
- Patent number 10,353,744
- Issue date Jul 16, 2019
- Hewlett Packard Enterprise Development LP
- Michael Bozich Calhoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power controller
- Patent number 9,405,339
- Issue date Aug 2, 2016
- Hewlett Packard Enterprise Development LP
- Ricardo Ernesto Espinoza-Ibarra
- G11 - INFORMATION STORAGE
Information Patent Grant
Rank sparing system and method
- Patent number 8,892,942
- Issue date Nov 18, 2014
- Hewlett-Packard Development Company, L.P.
- Lidia Warnes
- G11 - INFORMATION STORAGE
Information Patent Grant
Increasing the number of ranks per channel
- Patent number 8,539,145
- Issue date Sep 17, 2013
- Hewlett-Packard Development Company, L.P.
- Lidia Warnes
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel memory device rank selection
- Patent number 8,275,956
- Issue date Sep 25, 2012
- Hewlett-Packard Development Company, L.P.
- Lidia Warnes
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module including environmental optimization
- Patent number 8,225,031
- Issue date Jul 17, 2012
- Hewlett-Packard Development Company, L.P.
- Teddy Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module including voltage sense monitoring interface
- Patent number 8,018,753
- Issue date Sep 13, 2011
- Hewlett-Packard Development Company, L.P.
- Dennis Carr
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel memory device rank selection
- Patent number 7,996,602
- Issue date Aug 9, 2011
- Hewlett-Packard Development Company, L.P.
- Lidia Warnes
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential on-line termination
- Patent number 7,741,867
- Issue date Jun 22, 2010
- Hewlett-Packard Development Company, L.P.
- Dennis Carr
- G11 - INFORMATION STORAGE
Information Patent Grant
Communicating between a native fully buffered dual in-line memory m...
- Patent number 7,739,441
- Issue date Jun 15, 2010
- Hewlett-Packard Development Company, L.P.
- Teddy Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular DIMM carrier and riser slot
- Patent number 7,729,126
- Issue date Jun 1, 2010
- Hewlett-Packard Development Company, L.P.
- Michael Bozich Calhoun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Employing a native fully buffered dual in-line memory module protoc...
- Patent number 7,711,887
- Issue date May 4, 2010
- Hewlett-Packard Development Company, L.P.
- Lidia Warnes
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MESH CONFIGURATION NETWORK
- Publication number 20210014907
- Publication date Jan 14, 2021
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Mark Gordon Fraser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR ARCHITECTURE WITH SPECULATIVE BITS TO PREVENT CACHE VULNE...
- Publication number 20190332384
- Publication date Oct 31, 2019
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Michael Bozich Calhoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PROCESSOR CACHE TO AVOID SPECULATIVE VULNERABILITY
- Publication number 20190332379
- Publication date Oct 31, 2019
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Michael Bozich Calhoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM WIDE MANAGEABILITY
- Publication number 20160299792
- Publication date Oct 13, 2016
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Michael Bozich Calhoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR DISPLAY MODULE
- Publication number 20160203040
- Publication date Jul 14, 2016
- Hewlett-Packard Development Company, L.P.
- Michael Bozich Calhoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL MEMORY DEVICE RANK SELECTION
- Publication number 20110258400
- Publication date Oct 20, 2011
- Lidia Warnes
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL ON-LINE TERMINATION
- Publication number 20100109704
- Publication date May 6, 2010
- Dennis Carr
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION
- Publication number 20100115180
- Publication date May 6, 2010
- Teddy Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE
- Publication number 20100115179
- Publication date May 6, 2010
- Dennis Carr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular DIMM carrier and riser slot
- Publication number 20090035978
- Publication date Feb 5, 2009
- Michael Bozich Calhoun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Rank sparing system and method
- Publication number 20090031078
- Publication date Jan 29, 2009
- Lidia Warnes
- G11 - INFORMATION STORAGE

Michael Bozich Calhoun

Person

Patents Grantslast 30 patents

Dynamic processor cache to avoid speculative vulnerability

Mesh configuration network

System wide manageability

Power controller

Rank sparing system and method

Increasing the number of ranks per channel

Parallel memory device rank selection

Memory module including environmental optimization

Memory module including voltage sense monitoring interface

Parallel memory device rank selection

Differential on-line termination

Communicating between a native fully buffered dual in-line memory m...

Modular DIMM carrier and riser slot

Employing a native fully buffered dual in-line memory module protoc...

Patents Applicationslast 30 patents

MESH CONFIGURATION NETWORK

PROCESSOR ARCHITECTURE WITH SPECULATIVE BITS TO PREVENT CACHE VULNE...

DYNAMIC PROCESSOR CACHE TO AVOID SPECULATIVE VULNERABILITY

SYSTEM WIDE MANAGEABILITY

ERROR DISPLAY MODULE

PARALLEL MEMORY DEVICE RANK SELECTION

DIFFERENTIAL ON-LINE TERMINATION

MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION

MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE

Modular DIMM carrier and riser slot

Rank sparing system and method