Michael Chan

Person

Scarborough, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for reducing spatial overlap between routing...
- Patent number 9,564,394
- Issue date Feb 7, 2017
- Altera Corporation
- Aron Joseph Roth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for reducing crosstalk and twist region heigh...
- Patent number 9,153,531
- Issue date Oct 6, 2015
- Altera Corporation
- Aron Joseph Roth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric signal routing in a programmable logic device
- Patent number 8,643,399
- Issue date Feb 4, 2014
- Altera Corporation
- Tim Vanderhoek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 8,191,025
- Issue date May 29, 2012
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for facilitating effective and efficient optim...
- Patent number 7,712,067
- Issue date May 4, 2010
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 7,644,386
- Issue date Jan 5, 2010
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for facilitating effective and efficient optim...
- Patent number 7,257,795
- Issue date Aug 14, 2007
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 7,180,324
- Issue date Feb 20, 2007
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,965,249
- Issue date Nov 15, 2005
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for optimizing routing lines in a programmable lo...
- Patent number 6,895,570
- Issue date May 17, 2005
- Altera Corporation
- David M. Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible I/O routing resources
- Patent number 6,826,741
- Issue date Nov 30, 2004
- Altera Corporation
- Brian D. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Redundancy structures and methods in a programmable logic device
- Publication number 20050264318
- Publication date Dec 1, 2005
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with redundant circuitry
- Publication number 20030072185
- Publication date Apr 17, 2003
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for asymmetric routing lines
- Publication number 20020166106
- Publication date Nov 7, 2002
- David M. Lewis
- G06 - COMPUTING CALCULATING COUNTING

Michael Chan

Person

Patents Grantslast 30 patents

Methods and apparatus for reducing spatial overlap between routing...

Methods and apparatus for reducing crosstalk and twist region heigh...

Asymmetric signal routing in a programmable logic device

Redundancy structures and methods in a programmable logic device

Method and apparatus for facilitating effective and efficient optim...

Redundancy structures and methods in a programmable logic device

Method and apparatus for facilitating effective and efficient optim...

Redundancy structures and methods in a programmable logic device

Programmable logic device with redundant circuitry

System and method for optimizing routing lines in a programmable lo...

Flexible I/O routing resources

Patents Applicationslast 30 patents

Redundancy structures and methods in a programmable logic device

Programmable logic device with redundant circuitry

System and method for asymmetric routing lines