Michael E. Runas

Person

McKinney, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory with bit line capacitive loading
- Patent number 9,177,671
- Issue date Nov 3, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with bit line current injection
- Patent number 9,076,556
- Issue date Jul 7, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with redundant sense amplifier
- Patent number 9,013,933
- Issue date Apr 21, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with variable strength sense amplifier
- Patent number 8,953,395
- Issue date Feb 10, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Weak bit detection in a memory through variable development time
- Patent number 8,780,654
- Issue date Jul 15, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with bit line current injection
- Patent number 8,780,657
- Issue date Jul 15, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with redundant sense amplifier
- Patent number 8,780,650
- Issue date Jul 15, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse dynamic logic gates with mux-D scan functionality
- Patent number 8,677,199
- Issue date Mar 18, 2014
- Apple Inc.
- Michael R. Seningen
- G01 - MEASURING TESTING
Information Patent Grant
Memory with redundant sense amplifier
- Patent number 8,559,249
- Issue date Oct 15, 2013
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse dynamic logic gates with LSSD scan functionality
- Patent number 8,555,121
- Issue date Oct 8, 2013
- Apple Inc.
- Michael R. Seningen
- G01 - MEASURING TESTING
Information Patent Grant
Reduced voltage swing clock distribution
- Patent number 8,482,333
- Issue date Jul 9, 2013
- Apple Inc.
- Michael E. Runas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Charge recycling a 1 of N NDL gate with a time varying power supply
- Patent number 8,450,991
- Issue date May 28, 2013
- Apple Inc.
- Michael Runas
- G05 - CONTROLLING REGULATING
Information Patent Grant
Display controller with integrated half frame buffer and systems an...
- Patent number 5,945,974
- Issue date Aug 31, 1999
- Cirrus Logic, Inc.
- Sudhir Sharma
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Circuits, systems and methods for modifying data stored in a memory...
- Patent number 5,914,900
- Issue date Jun 22, 1999
- Cirrus Logic, Inc.
- Sudhir Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits, systems and methods for modifying data stored in a memory...
- Patent number 5,910,919
- Issue date Jun 8, 1999
- Cirrus Logic, Inc.
- Sudhir Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing circuitry with boolean logic
- Patent number 5,909,401
- Issue date Jun 1, 1999
- Cirrus Logic, Inc.
- Sudhir Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with an externally selectable-width I/O port and syst...
- Patent number 5,906,003
- Issue date May 18, 1999
- Cirrus Logic, Inc.
- Michael E. Runas
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with multiplexed input-output port and memory mapping...
- Patent number 5,835,965
- Issue date Nov 10, 1998
- Cirrus Logic, Inc.
- Ronald T. Taylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with multiplexed input-output port and systems and me...
- Patent number 5,829,016
- Issue date Oct 27, 1998
- Cirrus Logic, Inc.
- Sudhir Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits, systems and methods for modifying data stored in a memory...
- Patent number 5,732,024
- Issue date Mar 24, 1998
- Cirrus Logic, Inc.
- Sudhir Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance bus driving/receiving circuits, systems and methods
- Patent number 5,663,984
- Issue date Sep 2, 1997
- Cirrus Logic, Inc.
- Michael E. Runas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuits, systems and methods for controlling substrate bias in int...
- Patent number 5,612,644
- Issue date Mar 18, 1997
- Cirrus Logic Inc.
- Michael E. Runas
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits, systems and methods for the high speed transfer of data a...
- Patent number 5,596,291
- Issue date Jan 21, 1997
- Cirrus Logic, Inc.
- Michael E. Runas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits, systems and methods for testing ASIC and RAM memory devices
- Patent number 5,592,077
- Issue date Jan 7, 1997
- Cirrus Logic, Inc.
- Michael E. Runas
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits systems and methods for reducing power loss during transfe...
- Patent number 5,585,744
- Issue date Dec 17, 1996
- Cirrus Logic, Inc.
- Michael E. Runas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual bank memory system with output multiplexing and methods using...
- Patent number 5,570,320
- Issue date Oct 29, 1996
- Cirrus Logic, Inc.
- Michael E. Runas
- G11 - INFORMATION STORAGE
Information Patent Grant
Bus driver/receiver circuitry and systems and methods using the same
- Patent number 5,530,392
- Issue date Jun 25, 1996
- Cirrus Logic, Inc.
- Michael E. Runas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual bank memory and systems using the same
- Patent number 5,506,810
- Issue date Apr 9, 1996
- Cirrus Logic, Inc.
- Michael E. Runas
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits, systems and methods for improving page accesses and block...
- Patent number 5,500,819
- Issue date Mar 19, 1996
- Cirrus Logic, Inc.
- Michael E. Runas
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital voltage shifters and systems using the same
- Patent number 5,455,526
- Issue date Oct 3, 1995
- Cirrus Logic, Inc.
- Michael E. Runas
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MEMORY WITH REDUNDANT SENSE AMPLIFIER
- Publication number 20140269025
- Publication date Sep 18, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH BIT LINE CURRENT INJECTION
- Publication number 20140269124
- Publication date Sep 18, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR OPTIMIZING SENSE AMPLIFIER TIMING
- Publication number 20140032201
- Publication date Jan 30, 2014
- Edward M. McCombs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH REDUNDANT SENSE AMPLIFIER
- Publication number 20140010030
- Publication date Jan 9, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
WEAK BIT DETECTION IN A MEMORY THROUGH VARIABLE DEVELOPMENT TIME
- Publication number 20130265836
- Publication date Oct 10, 2013
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH REDUNDANT SENSE AMPLIFIER
- Publication number 20130258790
- Publication date Oct 3, 2013
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH BIT LINE CURRENT INJECTION
- Publication number 20130229877
- Publication date Sep 5, 2013
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH BIT LINE CAPACITIVE LOADING
- Publication number 20130223158
- Publication date Aug 29, 2013
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH VARIABLE STRENGTH SENSE AMPLIFIER
- Publication number 20130223159
- Publication date Aug 29, 2013
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE RECYCLING A 1 OF N NDL GATE WITH A TIME VARYING POWER SUPPLY
- Publication number 20130141073
- Publication date Jun 6, 2013
- Apple Inc.
- Michael E. Runas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED VOLTAGE SWING CLOCK DISTRIBUTION
- Publication number 20130093485
- Publication date Apr 18, 2013
- Michael E. Runas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Pulse Dynamic Logic Gates With Mux-D Scan Functionality
- Publication number 20110202805
- Publication date Aug 18, 2011
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSE DYNAMIC LOGIC GATES WITH LSSD SCAN FUNCTIONALITY
- Publication number 20110202810
- Publication date Aug 18, 2011
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARGE RECYCLING A 1 OF N NDL GATE WITH A TIME VARYING POWER SUPPLY
- Publication number 20100253311
- Publication date Oct 7, 2010
- Michael Runas
- G05 - CONTROLLING REGULATING

Michael E. Runas

Person

Patents Grantslast 30 patents

Memory with bit line capacitive loading

Memory with bit line current injection

Memory with redundant sense amplifier

Memory with variable strength sense amplifier

Weak bit detection in a memory through variable development time

Memory with bit line current injection

Memory with redundant sense amplifier

Pulse dynamic logic gates with mux-D scan functionality

Memory with redundant sense amplifier

Pulse dynamic logic gates with LSSD scan functionality

Reduced voltage swing clock distribution

Charge recycling a 1 of N NDL gate with a time varying power supply

Display controller with integrated half frame buffer and systems an...

Circuits, systems and methods for modifying data stored in a memory...

Circuits, systems and methods for modifying data stored in a memory...

Sensing circuitry with boolean logic

Memory device with an externally selectable-width I/O port and syst...

Memory system with multiplexed input-output port and memory mapping...

Memory system with multiplexed input-output port and systems and me...

Circuits, systems and methods for modifying data stored in a memory...

High performance bus driving/receiving circuits, systems and methods

Circuits, systems and methods for controlling substrate bias in int...

Circuits, systems and methods for the high speed transfer of data a...

Circuits, systems and methods for testing ASIC and RAM memory devices

Circuits systems and methods for reducing power loss during transfe...

Dual bank memory system with output multiplexing and methods using...

Bus driver/receiver circuitry and systems and methods using the same

Dual bank memory and systems using the same

Circuits, systems and methods for improving page accesses and block...

Digital voltage shifters and systems using the same

Patents Applicationslast 30 patents

MEMORY WITH REDUNDANT SENSE AMPLIFIER

MEMORY WITH BIT LINE CURRENT INJECTION

METHOD FOR OPTIMIZING SENSE AMPLIFIER TIMING

MEMORY WITH REDUNDANT SENSE AMPLIFIER

WEAK BIT DETECTION IN A MEMORY THROUGH VARIABLE DEVELOPMENT TIME

MEMORY WITH REDUNDANT SENSE AMPLIFIER

MEMORY WITH BIT LINE CURRENT INJECTION

MEMORY WITH BIT LINE CAPACITIVE LOADING

MEMORY WITH VARIABLE STRENGTH SENSE AMPLIFIER

CHARGE RECYCLING A 1 OF N NDL GATE WITH A TIME VARYING POWER SUPPLY

REDUCED VOLTAGE SWING CLOCK DISTRIBUTION

Pulse Dynamic Logic Gates With Mux-D Scan Functionality

PULSE DYNAMIC LOGIC GATES WITH LSSD SCAN FUNCTIONALITY

CHARGE RECYCLING A 1 OF N NDL GATE WITH A TIME VARYING POWER SUPPLY