Michael Fitton

Person

Menlo Park, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 12,141,088
- Issue date Nov 12, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused memory and arithmetic circuit
- Patent number 12,034,446
- Issue date Jul 9, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 12,014,150
- Issue date Jun 18, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 11,734,216
- Issue date Aug 22, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 11,650,792
- Issue date May 16, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 11,288,220
- Issue date Mar 29, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 11,256,476
- Issue date Feb 22, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused memory and arithmetic circuit
- Patent number 10,790,830
- Issue date Sep 29, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for matrix decompositions in programmable log...
- Patent number 9,483,233
- Issue date Nov 1, 2016
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for interfacing between hard logic and soft log...
- Patent number 9,000,802
- Issue date Apr 7, 2015
- Altera Corporation
- Michael Fitton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for interfacing between hard logic and soft log...
- Patent number 8,629,691
- Issue date Jan 14, 2014
- Altera Corporation
- Michael Fitton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for matrix decompositions in programmable log...
- Patent number 8,555,031
- Issue date Oct 8, 2013
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20240248682
- Publication date Jul 25, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED MEMORY AND ARITHMETIC CIRCUIT
- Publication number 20240235556
- Publication date Jul 11, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20230325334
- Publication date Oct 12, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20230244446
- Publication date Aug 3, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20220214990
- Publication date Jul 7, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20220129244
- Publication date Apr 28, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20210117356
- Publication date Apr 22, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20210042087
- Publication date Feb 11, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED MEMORY AND ARITHMETIC CIRCUIT
- Publication number 20200373925
- Publication date Nov 26, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...
- Publication number 20140125379
- Publication date May 8, 2014
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOG...
- Publication number 20140019500
- Publication date Jan 16, 2014
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOG...
- Publication number 20130140366
- Publication date Jun 6, 2013
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...
- Publication number 20120319730
- Publication date Dec 20, 2012
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING

Michael Fitton

Person

Patents Grantslast 30 patents

Cascade communications between FPGA tiles

Fused memory and arithmetic circuit

Multiple mode arithmetic circuit

Cascade communications between FPGA tiles

Multiple mode arithmetic circuit

Cascade communications between FPGA tiles

Multiple mode arithmetic circuit

Fused memory and arithmetic circuit

Methods and apparatus for matrix decompositions in programmable log...

Systems and methods for interfacing between hard logic and soft log...

Systems and methods for interfacing between hard logic and soft log...

Methods and apparatus for matrix decompositions in programmable log...

Patents Applicationslast 30 patents

Multiple Mode Arithmetic Circuit

FUSED MEMORY AND ARITHMETIC CIRCUIT

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

FUSED MEMORY AND ARITHMETIC CIRCUIT

SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...

METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOG...

METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOG...

SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...