Michael Gray

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical color decomposition of library cells with boundary-awa...
- Patent number 12,112,114
- Issue date Oct 8, 2024
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical color decomposition of process layers with shape and o...
- Patent number 11,822,867
- Issue date Nov 21, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked via rivets in chip hotspots
- Patent number 11,308,257
- Issue date Apr 19, 2022
- International Business Machines Corporation
- Dureseti Chidambarrao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fill techniques for avoiding Boolean DRC failures during cell place...
- Patent number 11,055,465
- Issue date Jul 6, 2021
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fin-based fill cell optimization
- Patent number 10,885,260
- Issue date Jan 5, 2021
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Criteria-based data push
- Patent number 10,069,926
- Issue date Sep 4, 2018
- International Business Machines Corporation
- Louie A. Dickens
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Selective boundary overlay insertion for hierarchical circuit design
- Patent number 9,971,861
- Issue date May 15, 2018
- International Business Machines Corporation
- Erwin Behnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Criteria-based data push
- Patent number 9,609,076
- Issue date Mar 28, 2017
- International Business Machines Corporation
- Louie A. Dickens
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital Frequency response analysis system and method useful for po...
- Patent number 9,562,951
- Issue date Feb 7, 2017
- Venable Corporation
- Manfred Trent
- G01 - MEASURING TESTING
Information Patent Grant
Criteria-based data push
- Patent number 9,456,045
- Issue date Sep 27, 2016
- International Business Machines Corporation
- Louie A. Dickens
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing color conflicts in triple patterning lithography
- Patent number 9,158,885
- Issue date Oct 13, 2015
- GLOBALFOUNDRIES, INC.
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel solving of layout optimization
- Patent number 8,555,229
- Issue date Oct 8, 2013
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post timing layout modification for performance
- Patent number 8,448,124
- Issue date May 21, 2013
- International Business Machines Corporation
- Uwe Fassnacht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to obtain a feasible integer solution in a hierarchical cir...
- Patent number 8,302,062
- Issue date Oct 30, 2012
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling two-dimensional constraints in integrated circuit layout
- Patent number 8,296,706
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive weighting method for layout optimization with multiple pri...
- Patent number 7,895,562
- Issue date Feb 22, 2011
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout optimization using parameterized cells
- Patent number 7,865,848
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Veit Gernhoefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC layout optimization to improve yield
- Patent number 7,818,694
- Issue date Oct 19, 2010
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining a feasible integer solution in a hierarchical circuit lay...
- Patent number 7,761,818
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Context aware sub-circuit layout modification
- Patent number 7,735,042
- Issue date Jun 8, 2010
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Point of sale integrator
- Patent number 7,575,159
- Issue date Aug 18, 2009
- Dell Products L.P.
- Karen Weisblatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for modeling dataflow systems and realization...
- Patent number 7,509,647
- Issue date Mar 24, 2009
- Annapolis Micro Systems, Inc.
- Robert L. Donaldson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC layout optimization to improve yield
- Patent number 7,503,020
- Issue date Mar 10, 2009
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for implementing overlay-based modification of VLSI design l...
- Patent number 7,490,308
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Christopher J. Gonzalez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimum layout perturbation-based artwork legalization with grid co...
- Patent number 7,484,197
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit yield enhancement using Voronoi diagrams
- Patent number 7,260,790
- Issue date Aug 21, 2007
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Point of sale integrator
- Patent number 7,243,844
- Issue date Jul 17, 2007
- Dell Products L.P.
- Karen Weisblatt
- G07 - CHECKING-DEVICES
Information Patent Grant
Cloned and original circuit shape merging
- Patent number 7,120,887
- Issue date Oct 10, 2006
- International Business Machines Corporation
- Henry A. Bonges, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit area minimization using scaling
- Patent number 7,117,456
- Issue date Oct 3, 2006
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for obtaining a feasible integer solution from a...
- Patent number 7,062,729
- Issue date Jun 13, 2006
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIERARCHICAL COLOR DECOMPOSITION OF PROCESS LAYERS WITH SHAPE AND O...
- Publication number 20230050539
- Publication date Feb 16, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL COLOR DECOMPOSITION OF LIBRARY CELLS WITH BOUNDARY-AWA...
- Publication number 20230050432
- Publication date Feb 16, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FILL TECHNIQUES FOR AVOIDING BOOLEAN DRC FAILURES DURING CELL PLACE...
- Publication number 20210064719
- Publication date Mar 4, 2021
- International Business Machines Corporation
- David WOLPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE BOUNDARY OVERLAY INSERTION FOR HIERARCHICAL CIRCUIT DESIGN
- Publication number 20170228486
- Publication date Aug 10, 2017
- International Business Machines Corporation
- Erwin Behnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITERIA-BASED DATA PUSH
- Publication number 20170078424
- Publication date Mar 16, 2017
- International Business Machines Corporation
- Louie A. Dickens
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CRITERIA-BASED DATA PUSH
- Publication number 20170078426
- Publication date Mar 16, 2017
- International Business Machines Corporation
- Louie A. Dickens
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital Frequency Response Analysis System and Method Useful for Po...
- Publication number 20150260801
- Publication date Sep 17, 2015
- Manfred Trent
- G01 - MEASURING TESTING
Information Patent Application
POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE
- Publication number 20130074025
- Publication date Mar 21, 2013
- International Business Machines Corporation
- Uwe Fassnacht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL SOLVING OF LAYOUT OPTIMIZATION
- Publication number 20120311517
- Publication date Dec 6, 2012
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEMATIC-BASED LAYOUT MIGRATION
- Publication number 20120233576
- Publication date Sep 13, 2012
- International Business Machines Corporation
- Geoffrey R. Barrows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT
- Publication number 20110265055
- Publication date Oct 27, 2011
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIR...
- Publication number 20100153892
- Publication date Jun 17, 2010
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRI...
- Publication number 20090158223
- Publication date Jun 18, 2009
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IC Layout Optimization to Improve Yield
- Publication number 20090100386
- Publication date Apr 16, 2009
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout Optimization Using Parameterized Cells
- Publication number 20090064061
- Publication date Mar 5, 2009
- Veit Gernhoefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION
- Publication number 20090037851
- Publication date Feb 5, 2009
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS
- Publication number 20090037850
- Publication date Feb 5, 2009
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAY...
- Publication number 20090031259
- Publication date Jan 29, 2009
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLS...
- Publication number 20080172638
- Publication date Jul 17, 2008
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IC Layout Optimization To Improve Yield
- Publication number 20070294648
- Publication date Dec 20, 2007
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MINIMUM LAYOUT PERTURBATION-BASED ARTWORK LEGALIZATION WITH GRID CO...
- Publication number 20070245283
- Publication date Oct 18, 2007
- Robert J Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Point of sale integrator
- Publication number 20070235530
- Publication date Oct 11, 2007
- Karen Weisblatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR IMPLEMENTING OVERLAY-BASED MODIFICATION OF VLSI DESIGN L...
- Publication number 20070234260
- Publication date Oct 4, 2007
- Christopher J. Gonzalez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Point of sale integrator
- Publication number 20070102514
- Publication date May 10, 2007
- Karen Weisblatt
- G07 - CHECKING-DEVICES
Information Patent Application
INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS
- Publication number 20060150130
- Publication date Jul 6, 2006
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for obtaining a feasible integer solution from a...
- Publication number 20060064661
- Publication date Mar 23, 2006
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLONED AND ORIGINAL CIRCUIT SHAPE MERGING
- Publication number 20050160390
- Publication date Jul 21, 2005
- International Business Machines Corporation
- Henry A. Bonges
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT AREA MINIMIZATION USING SCALING
- Publication number 20050125748
- Publication date Jun 9, 2005
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for modeling dataflow systems and realization...
- Publication number 20020178285
- Publication date Nov 28, 2002
- Annapolis Micro Systems, Inc.
- Robert L. Donaldson
- G06 - COMPUTING CALCULATING COUNTING

Michael Gray

Person

Patents Grantslast 30 patents

Hierarchical color decomposition of library cells with boundary-awa...

Hierarchical color decomposition of process layers with shape and o...

Stacked via rivets in chip hotspots

Fill techniques for avoiding Boolean DRC failures during cell place...

Fin-based fill cell optimization

Criteria-based data push

Selective boundary overlay insertion for hierarchical circuit design

Criteria-based data push

Digital Frequency response analysis system and method useful for po...

Criteria-based data push

Reducing color conflicts in triple patterning lithography

Parallel solving of layout optimization

Post timing layout modification for performance

Methods to obtain a feasible integer solution in a hierarchical cir...

Handling two-dimensional constraints in integrated circuit layout

Adaptive weighting method for layout optimization with multiple pri...

Layout optimization using parameterized cells

IC layout optimization to improve yield

Obtaining a feasible integer solution in a hierarchical circuit lay...

Context aware sub-circuit layout modification

Point of sale integrator

Method and apparatus for modeling dataflow systems and realization...

IC layout optimization to improve yield

Method for implementing overlay-based modification of VLSI design l...

Minimum layout perturbation-based artwork legalization with grid co...

Integrated circuit yield enhancement using Voronoi diagrams

Point of sale integrator

Cloned and original circuit shape merging

Circuit area minimization using scaling

Method and system for obtaining a feasible integer solution from a...

Patents Applicationslast 30 patents

HIERARCHICAL COLOR DECOMPOSITION OF PROCESS LAYERS WITH SHAPE AND O...

HIERARCHICAL COLOR DECOMPOSITION OF LIBRARY CELLS WITH BOUNDARY-AWA...

FILL TECHNIQUES FOR AVOIDING BOOLEAN DRC FAILURES DURING CELL PLACE...

SELECTIVE BOUNDARY OVERLAY INSERTION FOR HIERARCHICAL CIRCUIT DESIGN

CRITERIA-BASED DATA PUSH

CRITERIA-BASED DATA PUSH

Digital Frequency Response Analysis System and Method Useful for Po...

POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE

PARALLEL SOLVING OF LAYOUT OPTIMIZATION

SCHEMATIC-BASED LAYOUT MIGRATION

HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT

METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIR...

ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRI...

IC Layout Optimization to Improve Yield

Layout Optimization Using Parameterized Cells

CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION

POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS

OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAY...

METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLS...

IC Layout Optimization To Improve Yield

MINIMUM LAYOUT PERTURBATION-BASED ARTWORK LEGALIZATION WITH GRID CO...

Point of sale integrator

METHOD FOR IMPLEMENTING OVERLAY-BASED MODIFICATION OF VLSI DESIGN L...

Point of sale integrator

INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS

Method and system for obtaining a feasible integer solution from a...

CLONED AND ORIGINAL CIRCUIT SHAPE MERGING

CIRCUIT AREA MINIMIZATION USING SCALING

Method and apparatus for modeling dataflow systems and realization...