Michael HILL

Person

Gilbert, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Two stage multi-input multi-output regulator
- Patent number 12,074,514
- Issue date Aug 27, 2024
- Intel Corporation
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 11,804,426
- Issue date Oct 31, 2023
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate inductor having thermal interconnect structures
- Patent number 11,690,165
- Issue date Jun 27, 2023
- Intel Corporation
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and system with package stiffening magnetic inductor core...
- Patent number 11,527,489
- Issue date Dec 13, 2022
- Intel Corporation
- Michael J. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package structure having substrate thermal vent structures for indu...
- Patent number 11,437,346
- Issue date Sep 6, 2022
- Intel Corporation
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-level distributed clamps
- Patent number 11,380,652
- Issue date Jul 5, 2022
- Intel Corporation
- Beomseok Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate inductor having thermal interconnect structures
- Patent number 11,357,096
- Issue date Jun 7, 2022
- Intel Corporation
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package inductor having thermal solution structures
- Patent number 11,335,620
- Issue date May 17, 2022
- Intel Corporation
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, device and system to protect circuitry during a burn-in pro...
- Patent number 11,215,662
- Issue date Jan 4, 2022
- Intel Corporation
- William Lambert
- G01 - MEASURING TESTING
Information Patent Grant
Reconfigurable inductor
- Patent number 11,211,866
- Issue date Dec 28, 2021
- Intel Corporation
- William J. Lambert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 11,107,757
- Issue date Aug 31, 2021
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 10,672,693
- Issue date Jun 2, 2020
- Intel Corporation
- Sanka Ganesan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Apparatus and method to reduce power losses in an integrated voltag...
- Patent number 10,503,227
- Issue date Dec 10, 2019
- Intel Corporation
- Krishna Bharath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing a board assembly using test cards
- Patent number 10,175,296
- Issue date Jan 8, 2019
- Intel Corporation
- Joseph W. Batz
- G01 - MEASURING TESTING
Information Patent Grant
Development of the advanced component in cavity technology
- Patent number 10,159,152
- Issue date Dec 18, 2018
- Intel Corporation
- Ladd D. Campbell
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Tunable delay control of a power delivery network
- Patent number 10,122,209
- Issue date Nov 6, 2018
- Intel Corporation
- Ahmed Fouad Salama
- B06 - GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
Information Patent Grant
Apparatus and method to reduce power losses in an integrated voltag...
- Patent number 9,753,510
- Issue date Sep 5, 2017
- Intel Corporation
- Krishna Bharath
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Mechanism for facilitating and employing a magnetic grid array
- Patent number 9,461,431
- Issue date Oct 4, 2016
- Intel Corporation
- Gregorio R. Murtagian
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Techniques and configurations associated with a capductor assembly
- Patent number 9,230,944
- Issue date Jan 5, 2016
- Intel Corporation
- William J. Lambert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mechanism for facilitating and employing a magnetic grid array
- Patent number 9,118,143
- Issue date Aug 25, 2015
- Intel Corporation
- Gregorio R. Murtagian
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Package using array capacitor core
- Patent number 7,692,284
- Issue date Apr 6, 2010
- Intel Corporation
- Kimberly D. Eilert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Controlled equivalent series resistance capacitor
- Patent number 7,361,969
- Issue date Apr 22, 2008
- Intel Corporation
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Control of breakdown voltage for microelectronic packaging
- Patent number 7,324,317
- Issue date Jan 29, 2008
- Intel Corporation
- Michael J. Hill
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE SUBSTRATE INDUCTOR HAVING THERMAL INTERCONNECT STRUCTURES
- Publication number 20220240370
- Publication date Jul 28, 2022
- Intel Corporation
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO STAGE MULTI-INPUT MULTI-OUTPUT REGULATOR
- Publication number 20220094256
- Publication date Mar 24, 2022
- Intel Corporation
- Kaladhar RADHAKRISHNAN
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
- Publication number 20210351116
- Publication date Nov 11, 2021
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECONFIGURABLE INDUCTOR
- Publication number 20210036618
- Publication date Feb 4, 2021
- Intel Corporation
- WILLIAM J. Lambert
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
- Publication number 20200251411
- Publication date Aug 6, 2020
- Intel Corporation
- Sanka Ganesan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTI-LEVEL DISTRIBUTED CLAMPS
- Publication number 20200251448
- Publication date Aug 6, 2020
- Intel Corporation
- Beomseok Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUPPORTS HAVING INDUCTORS WITH MAGNETIC...
- Publication number 20200091053
- Publication date Mar 19, 2020
- Intel Corporation
- Sameer Paital
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE INDUCTOR HAVING THERMAL SOLUTION STRUCTURES
- Publication number 20200020652
- Publication date Jan 16, 2020
- Intel Corporation
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE SUBSTRATE INDUCTOR HAVING THERMAL INTERCONNECT STRUCTURES
- Publication number 20200015348
- Publication date Jan 9, 2020
- Intel Corporation
- Michael J. Hill
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PACKAGE STIFFENING MAGNETIC CORE
- Publication number 20200006250
- Publication date Jan 2, 2020
- Intel Corporation
- Michael J. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, DEVICE AND SYSTEM TO PROTECT CIRCUITRY DURING A BURN-IN PRO...
- Publication number 20200003829
- Publication date Jan 2, 2020
- Intel Corporation
- William Lambert
- G05 - CONTROLLING REGULATING
Information Patent Application
PACKAGE STRUCTURE HAVING SUBSTRATE THERMAL VENT STRUCTURES FOR INDU...
- Publication number 20200006287
- Publication date Jan 2, 2020
- Intel Corporation
- Michael J. HILL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
- Publication number 20190304887
- Publication date Oct 3, 2019
- Intel Corporation
- Sanka Ganesan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
TESTING A BOARD ASSEMBLY USING TEST CARDS
- Publication number 20180156868
- Publication date Jun 7, 2018
- Intel Corporation
- Joseph W. Batz
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAG...
- Publication number 20180101207
- Publication date Apr 12, 2018
- Intel Corporation
- Krishna Bharath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVELOPMENT OF THE ADVANCED COMPONENT IN CAVITY TECHNOLOGY
- Publication number 20170181286
- Publication date Jun 22, 2017
- Intel Corporation
- Ladd D. CAMPBELL
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAG...
- Publication number 20170060205
- Publication date Mar 2, 2017
- Intel Corporation
- Krishna Bharath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR FACILITATING AND EMPLOYING A MAGNETIC GRID ARRAY
- Publication number 20150318655
- Publication date Nov 5, 2015
- Intel Corporation
- GREGORIO R. MURTAGIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MECHANISM FOR FACILITATING AND EMPLOYING A MAGNETIC GRID ARRAY
- Publication number 20140187057
- Publication date Jul 3, 2014
- Gregorio R. Murtagian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded array capacitor with top and bottom exterior surface metal...
- Publication number 20080128854
- Publication date Jun 5, 2008
- Anne E. Augustine
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Embedded array capacitor with side terminals
- Publication number 20080079147
- Publication date Apr 3, 2008
- Michael J. Hill
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Package using array capacitor core
- Publication number 20070134925
- Publication date Jun 14, 2007
- Intel Corporation
- Kimberly D. Eilert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Controlled equivalent series resistance capacitor
- Publication number 20070007573
- Publication date Jan 11, 2007
- Michael J. Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Control of breakdown voltage for microelectronic packaging
- Publication number 20060044717
- Publication date Mar 2, 2006
- Michael J. Hill
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Michael HILL

Person

Patents Grantslast 30 patents

Two stage multi-input multi-output regulator

Integrated circuit structures in package substrates

Package substrate inductor having thermal interconnect structures

Apparatus and system with package stiffening magnetic inductor core...

Package structure having substrate thermal vent structures for indu...

Multi-level distributed clamps

Package substrate inductor having thermal interconnect structures

Package inductor having thermal solution structures

Method, device and system to protect circuitry during a burn-in pro...

Reconfigurable inductor

Integrated circuit structures in package substrates

Integrated circuit structures in package substrates

Apparatus and method to reduce power losses in an integrated voltag...

Testing a board assembly using test cards

Development of the advanced component in cavity technology

Tunable delay control of a power delivery network

Apparatus and method to reduce power losses in an integrated voltag...

Mechanism for facilitating and employing a magnetic grid array

Techniques and configurations associated with a capductor assembly

Mechanism for facilitating and employing a magnetic grid array

Package using array capacitor core

Controlled equivalent series resistance capacitor

Control of breakdown voltage for microelectronic packaging

Patents Applicationslast 30 patents

PACKAGE SUBSTRATE INDUCTOR HAVING THERMAL INTERCONNECT STRUCTURES

TWO STAGE MULTI-INPUT MULTI-OUTPUT REGULATOR

INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES

RECONFIGURABLE INDUCTOR

INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES

MULTI-LEVEL DISTRIBUTED CLAMPS

INTEGRATED CIRCUIT PACKAGE SUPPORTS HAVING INDUCTORS WITH MAGNETIC...

PACKAGE INDUCTOR HAVING THERMAL SOLUTION STRUCTURES

PACKAGE SUBSTRATE INDUCTOR HAVING THERMAL INTERCONNECT STRUCTURES

PACKAGE STIFFENING MAGNETIC CORE

METHOD, DEVICE AND SYSTEM TO PROTECT CIRCUITRY DURING A BURN-IN PRO...

PACKAGE STRUCTURE HAVING SUBSTRATE THERMAL VENT STRUCTURES FOR INDU...

INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES

TESTING A BOARD ASSEMBLY USING TEST CARDS

APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAG...

DEVELOPMENT OF THE ADVANCED COMPONENT IN CAVITY TECHNOLOGY

APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAG...

MECHANISM FOR FACILITATING AND EMPLOYING A MAGNETIC GRID ARRAY

MECHANISM FOR FACILITATING AND EMPLOYING A MAGNETIC GRID ARRAY

Embedded array capacitor with top and bottom exterior surface metal...

Embedded array capacitor with side terminals

Package using array capacitor core

Controlled equivalent series resistance capacitor

Control of breakdown voltage for microelectronic packaging