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Michael H.M. Chu
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Fremont, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Integrated circuit with bonding circuits for bonding memory control...
Patent number
9,558,131
Issue date
Jan 31, 2017
Altera Corporation
Jeffrey Schulz
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and system for operating a multi-port memory system
Patent number
9,343,124
Issue date
May 17, 2016
Altera Corporation
Caroline Ssu-Min Chen
G11 - INFORMATION STORAGE
Information
Patent Grant
Memory controllers with dynamic port priority assignment capabilities
Patent number
9,208,109
Issue date
Dec 8, 2015
Altera Corporation
Michael H. M. Chu
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Systems and methods for providing memory controllers with memory ac...
Patent number
9,032,162
Issue date
May 12, 2015
Altera Corporation
Ching-Chi Chang
G11 - INFORMATION STORAGE
Information
Patent Grant
Write-leveling implementation in programmable logic devices
Patent number
8,671,303
Issue date
Mar 11, 2014
Altera Corporation
Yan Chong
G11 - INFORMATION STORAGE
Information
Patent Grant
Write-leveling implementation in programmable logic devices
Patent number
8,122,275
Issue date
Feb 21, 2012
Altera Corporation
Yan Chong
G11 - INFORMATION STORAGE
Information
Patent Grant
Postamble timing for DDR memories
Patent number
7,990,783
Issue date
Aug 2, 2011
Altera Corporation
Philip Clarke
G11 - INFORMATION STORAGE
Information
Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
Patent number
7,990,786
Issue date
Aug 2, 2011
Altera Corporation
Michael H. M. Chu
G11 - INFORMATION STORAGE
Information
Patent Grant
PVT compensated auto-calibration scheme for DDR3
Patent number
7,983,094
Issue date
Jul 19, 2011
Altera Corporation
Manoj B. Roge
G11 - INFORMATION STORAGE
Information
Patent Grant
I/O block for high performance memory interfaces
Patent number
7,928,770
Issue date
Apr 19, 2011
Altera Corporation
Andrew Bellis
G11 - INFORMATION STORAGE
Information
Patent Grant
Postamble timing for DDR memories
Patent number
7,876,630
Issue date
Jan 25, 2011
Altera Corporation
Philip Clarke
G11 - INFORMATION STORAGE
Information
Patent Grant
Write-side calibration for data interface
Patent number
7,706,996
Issue date
Apr 27, 2010
Altera Corporation
Yan Chong
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
Patent number
7,593,273
Issue date
Sep 22, 2009
Altera Corporation
Michael H. M. Chu
G11 - INFORMATION STORAGE
Information
Patent Grant
PVT compensated auto-calibration scheme for DDR3
Patent number
7,590,008
Issue date
Sep 15, 2009
Altera Corporation
Manoj B. Roge
G11 - INFORMATION STORAGE
Information
Patent Grant
Dynamic control of memory interface timing
Patent number
7,589,556
Issue date
Sep 15, 2009
Altera Corporation
Johnson Tan
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Read-side calibration for data interface
Patent number
7,509,223
Issue date
Mar 24, 2009
Altera Corporation
Yan Chong
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Innovated technique to reduce memory interface write mode SSN in FPGA
Patent number
7,492,185
Issue date
Feb 17, 2009
Altera Corporation
Joseph Huang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Innovated technique to reduce memory interface write mode SSN in FPGA
Patent number
7,330,051
Issue date
Feb 12, 2008
Altera Corporation
Joseph Huang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Voltage ramp rate control circuit
Patent number
5,945,870
Issue date
Aug 31, 1999
Altera Corporation
Michael H. Chu
G11 - INFORMATION STORAGE
Information
Patent Grant
Programming programmable transistor devices using state machines
Patent number
5,869,980
Issue date
Feb 9, 1999
Altera Corporation
Michael Hsiao-Ming Chu
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Programming programmable transistor devices using state machines
Patent number
5,650,734
Issue date
Jul 22, 1997
Altera Corporation
Michael Hsiao-Ming Chu
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
MEMORY CONTROLLERS WITH DYNAMIC PORT PRIORITY ASSIGNMENT CAPABILITIES
Publication number
20120311277
Publication date
Dec 6, 2012
Michael H.M. Chu
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
Publication number
20120106264
Publication date
May 3, 2012
Altera Corporation
Yan Chong
G11 - INFORMATION STORAGE
Information
Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
Publication number
20090296503
Publication date
Dec 3, 2009
Altera Corporation
Michael H.M. Chu
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
Publication number
20080291758
Publication date
Nov 27, 2008
Altera Corporation
Michael H.M. Chu
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
Publication number
20080201597
Publication date
Aug 21, 2008
Altera Corporation
Yan Chong
G11 - INFORMATION STORAGE
Information
Patent Application
Read-Side Calibration for Data Interface
Publication number
20070282555
Publication date
Dec 6, 2007
Altera Corporation
Yan Chong
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Write-Side Calibration for Data Interface
Publication number
20070277071
Publication date
Nov 29, 2007
Altera Corporation
Yan Chong
G06 - COMPUTING CALCULATING COUNTING