Michael Hutton

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thermal management of integrated circuits
- Patent number 11,714,471
- Issue date Aug 1, 2023
- Intel Corporation
- Michael David Hutton
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Clock synthesis for frequency scaling in programmable logic designs
- Patent number 11,646,739
- Issue date May 9, 2023
- Intel Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid programmable many-core device with on-chip interconnect
- Patent number 11,256,656
- Issue date Feb 22, 2022
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for region-based error detection and management...
- Patent number 11,194,947
- Issue date Dec 7, 2021
- Intel Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock synthesis for frequency scaling in programmable logic designs
- Patent number 11,177,811
- Issue date Nov 16, 2021
- Intel Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermal management of integrated circuits
- Patent number 11,137,806
- Issue date Oct 5, 2021
- Intel Corporation
- Michael David Hutton
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Method and apparatus for implementing a system-level design tool fo...
- Patent number 10,678,979
- Issue date Jun 9, 2020
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid programmable many-core device with on-chip interconnect
- Patent number 10,635,631
- Issue date Apr 28, 2020
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable circuit having multiple sectors
- Patent number 10,523,207
- Issue date Dec 31, 2019
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
State visibility and manipulation in integrated circuits
- Patent number 10,515,165
- Issue date Dec 24, 2019
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with integrated network-on-chip
- Patent number 10,367,756
- Issue date Jul 30, 2019
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for embedding an error correction code in sto...
- Patent number 10,289,483
- Issue date May 14, 2019
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized error-detection and scheduling
- Patent number 10,248,484
- Issue date Apr 2, 2019
- Intel Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Omnibus logic element
- Patent number 10,177,766
- Issue date Jan 8, 2019
- Altera Corporation
- James Schleicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid programmable many-core device with on-chip interconnect
- Patent number 10,127,190
- Issue date Nov 13, 2018
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design instrumentation for state visualization
- Patent number 10,061,879
- Issue date Aug 28, 2018
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable storage circuits with embedded processing and control...
- Patent number 9,983,990
- Issue date May 29, 2018
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid programmable many-core device with on-chip interconnect
- Patent number 9,830,300
- Issue date Nov 28, 2017
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design instrumentation for state visualization
- Patent number 9,798,842
- Issue date Oct 24, 2017
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a system-level design tool fo...
- Patent number 9,740,808
- Issue date Aug 22, 2017
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array with integrated application specific...
- Patent number 9,705,506
- Issue date Jul 11, 2017
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
State visibility and manipulation in integrated circuits
- Patent number 9,697,318
- Issue date Jul 4, 2017
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for using scan storage circuits
- Patent number 9,588,176
- Issue date Mar 7, 2017
- Altera Corporation
- Michael Hutton
- G01 - MEASURING TESTING
Information Patent Grant
Configurable register circuitry for error detection and recovery
- Patent number 9,583,218
- Issue date Feb 28, 2017
- Altera Corporation
- Michael D. Hutton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuits with error handling capabilities
- Patent number 9,575,862
- Issue date Feb 21, 2017
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a system-level design tool fo...
- Patent number 9,507,883
- Issue date Nov 29, 2016
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Omnibus logic element
- Patent number 9,496,875
- Issue date Nov 15, 2016
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with integrated network-on-chip
- Patent number 9,479,456
- Issue date Oct 25, 2016
- Altera Corporation
- Michael David Hutton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable storage blocks with embedded first-in first-out and la...
- Patent number 9,478,272
- Issue date Oct 25, 2016
- Altera Corporation
- Richard Arthur Grenier
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid programmable many-core device with on-chip interconnect
- Patent number 9,471,537
- Issue date Oct 18, 2016
- Altera Corporation
- Michael D. Hutton
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
Large-Scale Accelerator System Energy Performance Optimization
- Publication number 20230119235
- Publication date Apr 20, 2023
- Google LLC
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20220224656
- Publication date Jul 14, 2022
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMAL MANAGEMENT OF INTEGRATED CIRCUITS
- Publication number 20220011838
- Publication date Jan 13, 2022
- Intel Corporation
- Michael David Hutton
- B60 - VEHICLES IN GENERAL
Information Patent Application
CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS
- Publication number 20220014204
- Publication date Jan 13, 2022
- Intel Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT
- Publication number 20200257651
- Publication date Aug 13, 2020
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Circuit Having Multiple Sectors
- Publication number 20200136624
- Publication date Apr 30, 2020
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20190215280
- Publication date Jul 11, 2019
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT
- Publication number 20190121783
- Publication date Apr 25, 2019
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR REGION-BASED ERROR DETECTION AND MANAGEMENT...
- Publication number 20190095570
- Publication date Mar 28, 2019
- Intel Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS
- Publication number 20190097637
- Publication date Mar 28, 2019
- Intel Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMAL MANAGEMENT OF INTEGRATED CIRCUITS
- Publication number 20190043737
- Publication date Feb 7, 2019
- Intel Corporation
- Michael David Hutton
- B60 - VEHICLES IN GENERAL
Information Patent Application
PRIORITIZED ERROR-DETECTION AND SCHEDULING
- Publication number 20180239665
- Publication date Aug 23, 2018
- Intel Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT
- Publication number 20180089139
- Publication date Mar 29, 2018
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN INSTRUMENTATION FOR STATE VISUALIZATION
- Publication number 20180004878
- Publication date Jan 4, 2018
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Implementing a System-Level Design Tool fo...
- Publication number 20170316120
- Publication date Nov 2, 2017
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS
- Publication number 20170262563
- Publication date Sep 14, 2017
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS
- Publication number 20170103157
- Publication date Apr 13, 2017
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Implementing a System-Level Design Tool fo...
- Publication number 20170046455
- Publication date Feb 16, 2017
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Logic Device With Integrated Network-On-Chip
- Publication number 20170041249
- Publication date Feb 9, 2017
- Altera Corporation
- Michael David Hutton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT
- Publication number 20170024355
- Publication date Jan 26, 2017
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN STO...
- Publication number 20160378599
- Publication date Dec 29, 2016
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN MEM...
- Publication number 20160294413
- Publication date Oct 6, 2016
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS
- Publication number 20160049941
- Publication date Feb 18, 2016
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method And Circuit For Scalable Cross Point Switching Using 3-D Die...
- Publication number 20150341037
- Publication date Nov 26, 2015
- Altera Corporation
- Jeffrey Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND TOOLS FOR DESIGNING INTEGRATED CIRCUITS WITH AUTO-PIPEL...
- Publication number 20150121319
- Publication date Apr 30, 2015
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR RESILIENT PACKAGED COMPONENTS
- Publication number 20150028918
- Publication date Jan 29, 2015
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Implementing a System-Level Design Tool fo...
- Publication number 20140379307
- Publication date Dec 25, 2014
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Programmable Many-Core Device with On-Chip Interconnect
- Publication number 20140281379
- Publication date Sep 18, 2014
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mapping Network Applications to a Hybrid Programmable Many-Core Device
- Publication number 20140282560
- Publication date Sep 18, 2014
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20140126572
- Publication date May 8, 2014
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING

Michael Hutton

Person

Patents Grantslast 30 patents

Thermal management of integrated circuits

Clock synthesis for frequency scaling in programmable logic designs

Hybrid programmable many-core device with on-chip interconnect

Systems and methods for region-based error detection and management...

Clock synthesis for frequency scaling in programmable logic designs

Thermal management of integrated circuits

Method and apparatus for implementing a system-level design tool fo...

Hybrid programmable many-core device with on-chip interconnect

Programmable circuit having multiple sectors

State visibility and manipulation in integrated circuits

Programmable logic device with integrated network-on-chip

Methods and apparatus for embedding an error correction code in sto...

Prioritized error-detection and scheduling

Omnibus logic element

Hybrid programmable many-core device with on-chip interconnect

Circuit design instrumentation for state visualization

Configurable storage circuits with embedded processing and control...

Hybrid programmable many-core device with on-chip interconnect

Circuit design instrumentation for state visualization

Method and apparatus for implementing a system-level design tool fo...

Field programmable gate array with integrated application specific...

State visibility and manipulation in integrated circuits

Techniques for using scan storage circuits

Configurable register circuitry for error detection and recovery

Integrated circuits with error handling capabilities

Method and apparatus for implementing a system-level design tool fo...

Omnibus logic element

Programmable logic device with integrated network-on-chip

Configurable storage blocks with embedded first-in first-out and la...

Hybrid programmable many-core device with on-chip interconnect

Patents Applicationslast 30 patents

Large-Scale Accelerator System Energy Performance Optimization

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

THERMAL MANAGEMENT OF INTEGRATED CIRCUITS

CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS

HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT

Programmable Circuit Having Multiple Sectors

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT

SYSTEMS AND METHODS FOR REGION-BASED ERROR DETECTION AND MANAGEMENT...

CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS

THERMAL MANAGEMENT OF INTEGRATED CIRCUITS

PRIORITIZED ERROR-DETECTION AND SCHEDULING

HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT

CIRCUIT DESIGN INSTRUMENTATION FOR STATE VISUALIZATION

Method and Apparatus for Implementing a System-Level Design Tool fo...

STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS

STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS

Method and Apparatus for Implementing a System-Level Design Tool fo...

Programmable Logic Device With Integrated Network-On-Chip

HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT

METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN STO...

METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN MEM...

PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS

Method And Circuit For Scalable Cross Point Switching Using 3-D Die...

METHODS AND TOOLS FOR DESIGNING INTEGRATED CIRCUITS WITH AUTO-PIPEL...

ERROR RESILIENT PACKAGED COMPONENTS

Method and Apparatus for Implementing a System-Level Design Tool fo...

Hybrid Programmable Many-Core Device with On-Chip Interconnect

Mapping Network Applications to a Hybrid Programmable Many-Core Device

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP